📄 bell.rpt
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# !_LC1_B4 & !_LC3_B2 & SetHrkey;
-- Node name is '|counter24:SU2|~273~2'
-- Equation name is '_LC4_B4', type is buried
-- synthesized logic cell
_LC4_B4 = LCELL( _EQ015);
_EQ015 = _LC2_B4 & _LC3_B6 & !_LC8_B2
# _LC2_B4 & _LC3_B6 & _LC7_B4;
-- Node name is '|counter24:SU2|~274~1'
-- Equation name is '_LC5_B2', type is buried
-- synthesized logic cell
_LC5_B2 = LCELL( _EQ016);
_EQ016 = !_LC1_B2 & _LC2_B2 & !_LC3_B4
# !_LC1_B2 & !_LC2_B2 & _LC3_B4;
-- Node name is '|counter24:SU2|:280'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = DFFE( _EQ017, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ017 = _LC6_B6 & !SetHrkey;
-- Node name is '|counter24:SU2|:281'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = DFFE( _EQ018, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ018 = _LC4_B6 & !SetHrkey;
-- Node name is '|counter24:SU2|:282'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ019, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ019 = _LC4_B4 & _LC6_B2
# _LC8_B2 & !SetHrkey;
-- Node name is '|counter24:SU2|:283'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ020, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ020 = _LC4_B4 & _LC5_B2
# _LC2_B2 & !SetHrkey;
-- Node name is '|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C20', type is buried
_LC5_C20 = LCELL( _EQ021);
_EQ021 = _LC4_C20 & _LC8_C20;
-- Node name is '|counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C20', type is buried
_LC7_C20 = LCELL( _EQ022);
_EQ022 = _LC4_C20 & _LC6_C20 & _LC8_C20;
-- Node name is '|counter60:SU1|counter6:UC1|:14'
-- Equation name is '_LC3_C20', type is buried
!_LC3_C20 = _LC3_C20~NOT;
_LC3_C20~NOT = LCELL( _EQ023);
_EQ023 = !_LC6_C20
# _LC4_C20
# _LC2_C20
# !_LC8_C20;
-- Node name is '|counter60:SU1|counter6:UC1|:41'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = DFFE( _EQ024, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ024 = _LC2_C20 & !_LC6_C13
# _LC2_C20 & !_LC3_C20 & !_LC7_C20
# !_LC2_C20 & !_LC3_C20 & _LC6_C13 & _LC7_C20;
-- Node name is '|counter60:SU1|counter6:UC1|:42'
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = DFFE( _EQ025, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ025 = !_LC6_C13 & _LC6_C20
# !_LC3_C20 & !_LC5_C20 & _LC6_C20
# !_LC3_C20 & _LC5_C20 & _LC6_C13 & !_LC6_C20;
-- Node name is '|counter60:SU1|counter6:UC1|:43'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = DFFE( _EQ026, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ026 = _LC4_C20 & !_LC6_C13
# !_LC3_C20 & _LC4_C20 & !_LC8_C20
# !_LC3_C20 & !_LC4_C20 & _LC6_C13 & _LC8_C20;
-- Node name is '|counter60:SU1|counter6:UC1|:44'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = DFFE( _EQ027, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ027 = _LC6_C13 & !_LC8_C20
# !_LC6_C13 & _LC8_C20;
-- Node name is '|counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = LCELL( _EQ028);
_EQ028 = _LC3_C13 & _LC5_C13 & _LC8_C13;
-- Node name is '|counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ029);
_EQ029 = !_LC5_C13 & _LC8_C13
# !_LC3_C13 & _LC8_C13
# _LC3_C13 & _LC5_C13 & !_LC8_C13;
-- Node name is '|counter60:SU1|counter10:UC0|:41'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = DFFE( _EQ030, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ030 = _LC2_C13 & !_LC6_C13 & !_LC7_C13
# !_LC2_C13 & !_LC6_C13 & _LC7_C13 & SetMinkey
# _LC2_C13 & !SetMinkey;
-- Node name is '|counter60:SU1|counter10:UC0|:42'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFFE( _EQ031, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ031 = _LC4_C13 & !_LC6_C13 & SetMinkey
# _LC8_C13 & !SetMinkey;
-- Node name is '|counter60:SU1|counter10:UC0|:43'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = DFFE( _EQ032, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ032 = !_LC3_C13 & _LC5_C13 & !_LC6_C13
# _LC3_C13 & !_LC5_C13 & !_LC6_C13 & SetMinkey
# _LC5_C13 & !SetMinkey;
-- Node name is '|counter60:SU1|counter10:UC0|:44'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = DFFE( _EQ033, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ033 = !_LC3_C13 & SetMinkey
# _LC3_C13 & !SetMinkey;
-- Node name is '|counter60:SU1|:12'
-- Equation name is '_LC6_C13', type is buried
!_LC6_C13 = _LC6_C13~NOT;
_LC6_C13~NOT = LCELL( _EQ034);
_EQ034 = _LC8_C13
# _LC5_C13
# !_LC2_C13
# !_LC3_C13;
-- Node name is ':56'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ035);
_EQ035 = Second0 & _500Hz
# !Second0 & _1kHz;
-- Node name is '~59~1'
-- Equation name is '~59~1', location is LC3_B8, type is buried.
-- synthesized logic cell
_LC3_B8 = LCELL( _EQ036);
_EQ036 = Hour0 & Hour5 & _LC1_B8 & _LC8_B2
# !Hour0 & Hour5 & !_LC1_B8 & _LC8_B2
# Hour0 & !Hour5 & _LC1_B8 & !_LC8_B2
# !Hour0 & !Hour5 & !_LC1_B8 & !_LC8_B2;
-- Node name is '~59~2'
-- Equation name is '~59~2', location is LC4_B8, type is buried.
-- synthesized logic cell
_LC4_B8 = LCELL( _EQ037);
_EQ037 = Hour3 & Hour4 & _LC2_B2 & _LC8_B4
# !Hour3 & Hour4 & _LC2_B2 & !_LC8_B4
# Hour3 & !Hour4 & !_LC2_B2 & _LC8_B4
# !Hour3 & !Hour4 & !_LC2_B2 & !_LC8_B4;
-- Node name is '~59~3'
-- Equation name is '~59~3', location is LC5_B6, type is buried.
-- synthesized logic cell
_LC5_B6 = LCELL( _EQ038);
_EQ038 = CtrlBell & Hour6 & _LC2_B6 & _LC4_B6
# CtrlBell & !Hour6 & _LC2_B6 & !_LC4_B6;
-- Node name is '~59~4'
-- Equation name is '~59~4', location is LC7_B6, type is buried.
-- synthesized logic cell
_LC7_B6 = LCELL( _EQ039);
_EQ039 = Hour7 & _LC2_C13 & _LC6_B6 & Minute3
# Hour7 & !_LC2_C13 & _LC6_B6 & !Minute3
# !Hour7 & _LC2_C13 & !_LC6_B6 & Minute3
# !Hour7 & !_LC2_C13 & !_LC6_B6 & !Minute3;
-- Node name is '~59~5'
-- Equation name is '~59~5', location is LC1_B6, type is buried.
-- synthesized logic cell
_LC1_B6 = LCELL( _EQ040);
_EQ040 = Hour2 & _LC1_B4 & _LC5_B6 & _LC7_B6
# !Hour2 & !_LC1_B4 & _LC5_B6 & _LC7_B6;
-- Node name is '~59~6'
-- Equation name is '~59~6', location is LC2_C22, type is buried.
-- synthesized logic cell
_LC2_C22 = LCELL( _EQ041);
_EQ041 = Hour1 & _LC3_B2 & _LC6_C20 & Minute6
# !Hour1 & !_LC3_B2 & _LC6_C20 & Minute6
# Hour1 & _LC3_B2 & !_LC6_C20 & !Minute6
# !Hour1 & !_LC3_B2 & !_LC6_C20 & !Minute6;
-- Node name is '~59~7'
-- Equation name is '~59~7', location is LC1_C20, type is buried.
-- synthesized logic cell
_LC1_C20 = LCELL( _EQ042);
_EQ042 = _LC4_C20 & _LC8_C20 & Minute4 & Minute5
# !_LC4_C20 & _LC8_C20 & Minute4 & !Minute5
# _LC4_C20 & !_LC8_C20 & !Minute4 & Minute5
# !_LC4_C20 & !_LC8_C20 & !Minute4 & !Minute5;
-- Node name is '~59~8'
-- Equation name is '~59~8', location is LC1_C13, type is buried.
-- synthesized logic cell
_LC1_C13 = LCELL( _EQ043);
_EQ043 = _LC5_C13 & _LC8_C13 & Minute1 & Minute2
# _LC5_C13 & !_LC8_C13 & Minute1 & !Minute2
# !_LC5_C13 & _LC8_C13 & !Minute1 & Minute2
# !_LC5_C13 & !_LC8_C13 & !Minute1 & !Minute2;
-- Node name is '~59~9'
-- Equation name is '~59~9', location is LC3_C22, type is buried.
-- synthesized logic cell
_LC3_C22 = LCELL( _EQ044);
_EQ044 = _LC2_C20 & _LC3_C13 & Minute0 & Minute7
# _LC2_C20 & !_LC3_C13 & !Minute0 & Minute7
# !_LC2_C20 & _LC3_C13 & Minute0 & !Minute7
# !_LC2_C20 & !_LC3_C13 & !Minute0 & !Minute7;
-- Node name is '~59~10'
-- Equation name is '~59~10', location is LC1_C22, type is buried.
-- synthesized logic cell
_LC1_C22 = LCELL( _EQ045);
_EQ045 = _LC1_C13 & _LC1_C20 & _LC2_C22 & _LC3_C22;
-- Node name is ':59'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = LCELL( _EQ046);
_EQ046 = _LC1_B6 & _LC1_C22 & _LC3_B8 & _LC4_B8;
Project Information i:\workhard\bell.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,507K
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