📄 bell.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: i:\workhard\bell.rpt
bell
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 04 AND2 0 3 0 1 |counter24:SU2|lpm_add_sub:297|addcore:adder|:59
- 3 - B 06 AND2 s 0 2 0 1 |counter24:SU2|~104~1
- 7 - B 04 AND2 s 0 4 0 2 |counter24:SU2|~104~2
- 5 - B 04 OR2 0 2 0 2 |counter24:SU2|:142
- 1 - B 02 AND2 0 4 0 4 |counter24:SU2|:149
- 3 - B 04 OR2 ! 0 4 0 4 |counter24:SU2|:155
- 4 - B 02 OR2 0 4 0 1 |counter24:SU2|:180
- 7 - B 02 AND2 s 0 3 0 2 |counter24:SU2|~190~1
- 8 - B 04 DFFE + 1 2 1 4 |counter24:SU2|:207
- 1 - B 04 DFFE + 1 2 1 5 |counter24:SU2|:208
- 3 - B 02 DFFE + 1 2 1 6 |counter24:SU2|:209
- 1 - B 08 DFFE + 1 1 1 5 |counter24:SU2|:210
- 6 - B 02 OR2 0 4 0 1 |counter24:SU2|:261
- 2 - B 04 OR2 s 1 3 0 1 |counter24:SU2|~273~1
- 4 - B 04 OR2 s 0 4 0 5 |counter24:SU2|~273~2
- 5 - B 02 OR2 s 0 3 0 1 |counter24:SU2|~274~1
- 6 - B 06 DFFE + 1 0 1 3 |counter24:SU2|:280
- 4 - B 06 DFFE + 1 0 1 3 |counter24:SU2|:281
- 8 - B 02 DFFE + 1 2 1 4 |counter24:SU2|:282
- 2 - B 02 DFFE + 1 2 1 4 |counter24:SU2|:283
- 5 - C 20 AND2 0 2 0 1 |counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:55
- 7 - C 20 AND2 0 3 0 1 |counter60:SU1|counter6:UC1|lpm_add_sub:45|addcore:adder|:59
- 3 - C 20 OR2 ! 0 4 0 3 |counter60:SU1|counter6:UC1|:14
- 2 - C 20 DFFE + 0 3 1 2 |counter60:SU1|counter6:UC1|:41
- 6 - C 20 DFFE + 0 3 1 3 |counter60:SU1|counter6:UC1|:42
- 4 - C 20 DFFE + 0 3 1 4 |counter60:SU1|counter6:UC1|:43
- 8 - C 20 DFFE + 0 1 1 5 |counter60:SU1|counter6:UC1|:44
- 7 - C 13 AND2 0 3 0 1 |counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|:59
- 4 - C 13 OR2 0 3 0 1 |counter60:SU1|counter10:UC0|lpm_add_sub:45|addcore:adder|:68
- 2 - C 13 DFFE + 1 2 1 2 |counter60:SU1|counter10:UC0|:41
- 8 - C 13 DFFE + 1 2 1 4 |counter60:SU1|counter10:UC0|:42
- 5 - C 13 DFFE + 1 2 1 4 |counter60:SU1|counter10:UC0|:43
- 3 - C 13 DFFE + 1 0 1 5 |counter60:SU1|counter10:UC0|:44
- 6 - C 13 OR2 ! 0 4 0 7 |counter60:SU1|:12
- 2 - B 06 OR2 3 0 0 1 :56
- 3 - B 08 OR2 s 2 2 0 1 ~59~1
- 4 - B 08 OR2 s 2 2 0 1 ~59~2
- 5 - B 06 OR2 s 2 2 0 1 ~59~3
- 7 - B 06 OR2 s 2 2 0 1 ~59~4
- 1 - B 06 OR2 s 1 3 0 1 ~59~5
- 2 - C 22 OR2 s 2 2 0 1 ~59~6
- 1 - C 20 OR2 s 2 2 0 1 ~59~7
- 1 - C 13 OR2 s 2 2 0 1 ~59~8
- 3 - C 22 OR2 s 2 2 0 1 ~59~9
- 1 - C 22 AND2 s 0 4 0 1 ~59~10
- 2 - B 08 AND2 0 4 1 0 :59
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: i:\workhard\bell.rpt
bell
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 8/ 96( 8%) 18/ 48( 37%) 0/ 48( 0%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 7/ 96( 7%) 0/ 48( 0%) 10/ 48( 20%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: i:\workhard\bell.rpt
bell
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 _1Hz
Device-Specific Information: i:\workhard\bell.rpt
bell
** EQUATIONS **
CtrlBell : INPUT;
Hour0 : INPUT;
Hour1 : INPUT;
Hour2 : INPUT;
Hour3 : INPUT;
Hour4 : INPUT;
Hour5 : INPUT;
Hour6 : INPUT;
Hour7 : INPUT;
Minute0 : INPUT;
Minute1 : INPUT;
Minute2 : INPUT;
Minute3 : INPUT;
Minute4 : INPUT;
Minute5 : INPUT;
Minute6 : INPUT;
Minute7 : INPUT;
Second0 : INPUT;
SetHrkey : INPUT;
SetMinkey : INPUT;
_1Hz : INPUT;
_1kHz : INPUT;
_500Hz : INPUT;
-- Node name is 'Alarm_clock'
-- Equation name is 'Alarm_clock', type is output
Alarm_clock = _LC2_B8;
-- Node name is 'Set_Hr0'
-- Equation name is 'Set_Hr0', type is output
Set_Hr0 = _LC1_B8;
-- Node name is 'Set_Hr1'
-- Equation name is 'Set_Hr1', type is output
Set_Hr1 = _LC3_B2;
-- Node name is 'Set_Hr2'
-- Equation name is 'Set_Hr2', type is output
Set_Hr2 = _LC1_B4;
-- Node name is 'Set_Hr3'
-- Equation name is 'Set_Hr3', type is output
Set_Hr3 = _LC8_B4;
-- Node name is 'Set_Hr4'
-- Equation name is 'Set_Hr4', type is output
Set_Hr4 = _LC2_B2;
-- Node name is 'Set_Hr5'
-- Equation name is 'Set_Hr5', type is output
Set_Hr5 = _LC8_B2;
-- Node name is 'Set_Hr6'
-- Equation name is 'Set_Hr6', type is output
Set_Hr6 = _LC4_B6;
-- Node name is 'Set_Hr7'
-- Equation name is 'Set_Hr7', type is output
Set_Hr7 = _LC6_B6;
-- Node name is 'Set_Min0'
-- Equation name is 'Set_Min0', type is output
Set_Min0 = _LC3_C13;
-- Node name is 'Set_Min1'
-- Equation name is 'Set_Min1', type is output
Set_Min1 = _LC5_C13;
-- Node name is 'Set_Min2'
-- Equation name is 'Set_Min2', type is output
Set_Min2 = _LC8_C13;
-- Node name is 'Set_Min3'
-- Equation name is 'Set_Min3', type is output
Set_Min3 = _LC2_C13;
-- Node name is 'Set_Min4'
-- Equation name is 'Set_Min4', type is output
Set_Min4 = _LC8_C20;
-- Node name is 'Set_Min5'
-- Equation name is 'Set_Min5', type is output
Set_Min5 = _LC4_C20;
-- Node name is 'Set_Min6'
-- Equation name is 'Set_Min6', type is output
Set_Min6 = _LC6_C20;
-- Node name is 'Set_Min7'
-- Equation name is 'Set_Min7', type is output
Set_Min7 = _LC2_C20;
-- Node name is '|counter24:SU2|lpm_add_sub:297|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ001);
_EQ001 = _LC1_B4 & _LC1_B8 & _LC3_B2;
-- Node name is '|counter24:SU2|~104~1'
-- Equation name is '_LC3_B6', type is buried
-- synthesized logic cell
_LC3_B6 = LCELL( _EQ002);
_EQ002 = !_LC4_B6 & !_LC6_B6;
-- Node name is '|counter24:SU2|~104~2'
-- Equation name is '_LC7_B4', type is buried
-- synthesized logic cell
_LC7_B4 = LCELL( _EQ003);
_EQ003 = !_LC1_B4 & !_LC2_B2 & _LC5_B4 & !_LC8_B4;
-- Node name is '|counter24:SU2|:142'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = LCELL( _EQ004);
_EQ004 = !_LC3_B2
# !_LC1_B8;
-- Node name is '|counter24:SU2|:149'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ005);
_EQ005 = !_LC4_B6 & !_LC6_B6 & _LC7_B4 & _LC8_B2;
-- Node name is '|counter24:SU2|:155'
-- Equation name is '_LC3_B4', type is buried
!_LC3_B4 = _LC3_B4~NOT;
_LC3_B4~NOT = LCELL( _EQ006);
_EQ006 = !_LC8_B4
# _LC1_B4
# _LC3_B2
# !_LC1_B8;
-- Node name is '|counter24:SU2|:180'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ007);
_EQ007 = !_LC1_B8 & _LC3_B2 & !_LC3_B4
# _LC1_B2 & !_LC1_B8 & _LC3_B2
# _LC1_B8 & !_LC3_B2 & !_LC3_B4
# _LC1_B2 & _LC1_B8 & !_LC3_B2;
-- Node name is '|counter24:SU2|~190~1'
-- Equation name is '_LC7_B2', type is buried
-- synthesized logic cell
_LC7_B2 = LCELL( _EQ008);
_EQ008 = !_LC1_B2 & !_LC3_B4 & _LC4_B4;
-- Node name is '|counter24:SU2|:207'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ009, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ009 = !_LC6_B4 & _LC7_B2 & _LC8_B4
# _LC6_B4 & _LC7_B2 & !_LC8_B4
# _LC8_B4 & !SetHrkey;
-- Node name is '|counter24:SU2|:208'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = DFFE( _EQ010, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ010 = _LC1_B4 & _LC5_B4 & _LC7_B2
# !_LC1_B4 & !_LC5_B4 & _LC7_B2
# _LC1_B4 & !SetHrkey;
-- Node name is '|counter24:SU2|:209'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = DFFE( _EQ011, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ011 = _LC4_B2 & _LC4_B4
# _LC3_B2 & !SetHrkey;
-- Node name is '|counter24:SU2|:210'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = DFFE( _EQ012, GLOBAL( _1Hz), VCC, VCC, VCC);
_EQ012 = !_LC1_B8 & _LC4_B4
# _LC1_B8 & !SetHrkey;
-- Node name is '|counter24:SU2|:261'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ013);
_EQ013 = !_LC2_B2 & _LC8_B2
# _LC2_B2 & _LC3_B4 & !_LC8_B2
# !_LC3_B4 & _LC8_B2
# _LC1_B2;
-- Node name is '|counter24:SU2|~273~1'
-- Equation name is '_LC2_B4', type is buried
-- synthesized logic cell
_LC2_B4 = LCELL( _EQ014);
_EQ014 = !_LC8_B4 & SetHrkey
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