notetbs.vhd

来自「乐曲演奏设计电路,可演奏不同的乐曲.长时间播放音乐.」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
   entity notetabs is
      port(clk:in std_logic;  
                toneindex:out std_logic_vector(3 downto 0)) ;
  end notetabs;
    architecture one of notetabs is
     component music
        port(address:in std_logic_vector(7 downto 0);
                  clock:in std_logic;
                   q:out std_logic_vector(3 downto 0));
     end component;
        signal counter:std_logic_vector(7 downto 0);
     begin
        cnt8: process(clk,counter)
           begin
              if counter=138 then counter<="00000000";
              elsif (clk'event and clk='1')  then counter<=counter+1;
              end if;
         end process;
  u1:  music port map(address=>counter,q=>toneindex,clock=>clk);
 end;