songer.tan.rpt
来自「乐曲演奏设计电路,可演奏不同的乐曲.长时间播放音乐.」· RPT 代码 · 共 285 行 · 第 1/5 页
RPT
285 行
Timing Analyzer report for songer
Mon Nov 10 22:42:08 2008
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk12mh'
6. Clock Setup: 'clk8hz'
7. Clock Setup: 'altera_internal_jtag~TCKUTAP'
8. Clock Hold: 'clk8hz'
9. tsu
10. tco
11. tpd
12. th
13. Timing Analyzer Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu ; N/A ; None ; -0.117 ns ; altera_internal_jtag~TMSUTAP ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] ; -- ; altera_internal_jtag~TCKUTAP ; 0 ;
; Worst-case tco ; N/A ; None ; 20.304 ns ; tonetaba:u2|code[1] ; code1[1] ; clk8hz ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 2.124 ns ; altera_internal_jtag~TDO ; altera_reserved_tdo ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 3.001 ns ; altera_internal_jtag ; notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7] ; -- ; altera_internal_jtag~TCKUTAP ; 0 ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A ; None ; 139.35 MHz ( period = 7.176 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] ; sld_hub:sld_hub_inst|hub_tdo ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0 ;
; Clock Setup: 'clk12mh' ; N/A ; None ; 195.69 MHz ( period = 5.110 ns ) ; speakera:u3|\genspks:count11[3] ; speakera:u3|\genspks:count11[3] ; clk12mh ; clk12mh ; 0 ;
; Clock Setup: 'clk8hz' ; N/A ; None ; 197.01 MHz ( period = 5.076 ns ) ; notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_datain_reg3 ; notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_memory_reg3 ; clk8hz ; clk8hz ; 0 ;
; Clock Hold: 'clk8hz' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; notetabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_el51:auto_generated|altsyncram_ldj2:altsyncram1|ram_block3a1~porta_address_reg0 ; tonetaba:u2|tone[3] ; clk8hz ; clk8hz ; 120 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 120 ;
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