shiftdata.v

来自「vhdl编程 实现移位寄存器 左移动和右移动」· Verilog 代码 · 共 67 行

//--------------------------------------------------------------------------------------------------
//
// Title       : shiftdata
// Design      : exp1
// Author      : liwei
// Company     : buaa
//
//-------------------------------------------------------------------------------------------------
//
// File        : shiftdata.v
// Generated   : Tue Apr 25 23:09:40 2006
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1 ns / 1 ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {shiftdata}}
module shiftdata ( left_right ,load ,clr ,clk ,DIN ,DOUT );

input left_right ;
wire left_right ;
input load ;
wire load ;
input clr ;
wire clr ;
input clk ;
wire clk ;
input [3:0] DIN ;
wire [3:0] DIN ;

output [3:0] DOUT ;
wire [3:0] DOUT ;
reg [3:0] data_r;
//}} End of automatically maintained section	 

assign 	  DOUT	= data_r  ;

// -- edit by liwei -- // 	  

always @ ( posedge clk or posedge clr or posedge load )	  
	begin 
	if ( clr == 1)
		data_r <= 0;
	else if (load )	
		data_r <= DIN;
	else begin
		if ( left_right)   
			begin 
			data_r <= (data_r<<1);
			data_r[0] <= 0;	
			end
		else begin
			data_r <= (data_r>>1);
			data_r[3] <= 0;	 
			end
		end	  
	end

endmodule