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📄 chip_c8051.symb

📁 USB v1.1 RTL and design specification
💻 SYMB
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$VAR1 = {
          '-main' => {
                       'std_logic' => {},
                       'romfile' => {
                                      '-size' => '',
                                      '-type' => 'string',
                                      '-init' => '"introm.hex"',
                                      '-port' => '',
                                      '-right' => '',
                                      '-name' => 'ROMFILE',
                                      '-range' => '',
                                      '-class' => 'constant',
                                      '-left' => '',
                                      '-val' => 'ROMFILE'
                                    },
                       'xtal1' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'xtal1',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'xtal1'
                                  },
                       'xtal2' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'xtal2',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'xtal2'
                                  },
                       'work' => {},
                       'ale' => {
                                  '-size' => '',
                                  '-type' => 'std_logic',
                                  '-init' => '',
                                  '-port' => '',
                                  '-right' => '',
                                  '-name' => 'ale',
                                  '-range' => '',
                                  '-class' => 'port',
                                  '-left' => '',
                                  '-val' => 'ale'
                                },
                       'chip_c8051' => {
                                         '-size' => '',
                                         '-type' => '',
                                         '-init' => '',
                                         '-port' => '',
                                         '-name' => 'CHIP_C8051',
                                         '-range' => '',
                                         '-class' => '',
                                         '-val' => 'CHIP_C8051'
                                       },
                       'std_logic_vector' => {},
                       'ieee' => {},
                       'string' => {
                                     '-size' => '',
                                     '-type' => '',
                                     '-init' => '',
                                     '-port' => '',
                                     '-name' => 'STRING',
                                     '-range' => '',
                                     '-class' => '',
                                     '-val' => 'STRING'
                                   },
                       'romsize' => {
                                      '-size' => '',
                                      '-type' => 'integer',
                                      '-init' => '14',
                                      '-port' => '',
                                      '-right' => '',
                                      '-name' => 'ROMSIZE',
                                      '-range' => '',
                                      '-class' => 'constant',
                                      '-left' => '',
                                      '-val' => 'ROMSIZE'
                                    },
                       'ea' => {
                                 '-size' => '',
                                 '-type' => 'std_logic',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '',
                                 '-name' => 'ea',
                                 '-range' => '',
                                 '-class' => 'port',
                                 '-left' => '',
                                 '-val' => 'ea'
                               },
                       'integer' => {
                                      '-size' => '',
                                      '-type' => '',
                                      '-init' => '',
                                      '-port' => '',
                                      '-name' => 'INTEGER',
                                      '-range' => '',
                                      '-class' => '',
                                      '-val' => 'INTEGER'
                                    },
                       'std_logic_1164' => {},
                       'p0' => {
                                 '-size' => '',
                                 '-type' => 'std_logic_vector',
                                 '-val1' => 'p0_xhdl0',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '0',
                                 '-name' => 'p0',
                                 '-range' => '[7:0]',
                                 '-class' => 'port',
                                 '-left' => '7',
                                 '-val' => 'p0'
                               },
                       'reset' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'reset',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'reset'
                                  },
                       'p1' => {
                                 '-size' => '',
                                 '-type' => 'std_logic_vector',
                                 '-val1' => 'p1_xhdl1',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '0',
                                 '-name' => 'p1',
                                 '-range' => '[7:0]',
                                 '-class' => 'port',
                                 '-left' => '7',
                                 '-val' => 'p1'
                               },
                       'p2' => {
                                 '-size' => '',
                                 '-type' => 'std_logic_vector',
                                 '-val1' => 'p2_xhdl2',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '0',
                                 '-name' => 'p2',
                                 '-range' => '[7:0]',
                                 '-class' => 'port',
                                 '-left' => '7',
                                 '-val' => 'p2'
                               },
                       'p3' => {
                                 '-size' => '',
                                 '-type' => 'std_logic_vector',
                                 '-val1' => 'p3_xhdl3',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '0',
                                 '-name' => 'p3',
                                 '-range' => '[7:0]',
                                 '-class' => 'port',
                                 '-left' => '7',
                                 '-val' => 'p3'
                               },
                       'ramsize' => {
                                      '-size' => '',
                                      '-type' => 'integer',
                                      '-init' => '8',
                                      '-port' => '',
                                      '-right' => '',
                                      '-name' => 'RAMSIZE',
                                      '-range' => '',
                                      '-class' => 'constant',
                                      '-left' => '',
                                      '-val' => 'RAMSIZE'
                                    },
                       'psen' => {
                                   '-size' => '',
                                   '-type' => 'std_logic',
                                   '-init' => '',
                                   '-port' => '',
                                   '-right' => '',
                                   '-name' => 'psen',
                                   '-range' => '',
                                   '-class' => 'port',
                                   '-left' => '',
                                   '-val' => 'psen'
                                 }
                     }
        };

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