chip_oci.code

USB v1.1 RTL and design specification

$VAR1 = {
          '-flags' => {
                        'defines_included' => undef
                      },
          '-inits' => undef,
          '-design_name' => 'CHIP_OCI',
          '-code' => '//*******************************************************************--
// Copyright (c) 1999-2001  Evatronix SA                             --
//*******************************************************************--
// Please review the terms of the license agreement before using     --
// this file. If you are not an authorized user, please destroy this --
// source code file and notify Evatronix SA immediately that you     --
// inadvertently received an unauthorized copy.                      --
//*******************************************************************--
//---------------------------------------------------------------------
// Project name         : C8051
// Project description  : C8051 Microcontroller Unit
//
// File name            : CHIPOCI.VHD
// File contents        : Entity CHIP_OCI
//                        Architecture SIM of CHIP_OCI
// Purpose              : On-Chip Instrumentation
//
// Destination library  : C8051_LIB
// Dependencies         : IEEE.STD_LOGIC_1164
//
// Design Engineer      : D.K.
// Quality Engineer     : M.B.
// Version              : 3.01
// Last modification    : 2001-10-01
//---------------------------------------------------------------------
module CHIP_OCI (clk, rst, addrbus, databusi, romoe, ramaddr, ramdatai, ramdatao, ramwe, ramoe, sfraddr, sfrdatai, sfrdatao, sfrwe, sfroe, accreg, fetch, flush, debugack, debugreq, debugstep, debugprog);

鴌nput clk; 
input rst; 
input[13:0] addrbus; 
input[7:0] databusi; 
input romoe; 
input[7:0] ramaddr; 
input[7:0] ramdatai; 
input[7:0] ramdatao; 
input ramwe; // Memory write enable
input ramoe; // Memory output enable
input[6:0] sfraddr; 
input[7:0] sfrdatai; 
input[7:0] sfrdatao; 
input sfrwe; // Register write enable
input sfroe; // Register output enable
input[7:0] accreg; 
input fetch; // branch intruction fetch
input flush; // no-branch instruction fetch
input debugack; // debugger acknowlege
output debugreq; // debug mode request
wire debugreq;
output debugstep; // debug mode single step
wire debugstep;
output debugprog; 
wire debugprog;

'
        };