internal_program_memory.symb

USB v1.1 RTL and design specification

$VAR1 = {
          '-main' => {
                       'std_logic' => {},
                       'string' => {
                                     '-size' => '',
                                     '-type' => '',
                                     '-init' => '',
                                     '-port' => '',
                                     '-name' => 'STRING',
                                     '-range' => '',
                                     '-class' => '',
                                     '-val' => 'STRING'
                                   },
                       'romfile' => {
                                      '-size' => '',
                                      '-type' => 'string',
                                      '-init' => '"introm.hex"',
                                      '-port' => '',
                                      '-right' => '',
                                      '-name' => 'ROMFILE',
                                      '-range' => '',
                                      '-class' => 'constant',
                                      '-left' => '',
                                      '-val' => 'ROMFILE'
                                    },
                       'addrwidth' => {
                                        '-size' => '',
                                        '-type' => 'integer',
                                        '-init' => '12',
                                        '-port' => '',
                                        '-right' => '',
                                        '-name' => 'ADDRWIDTH',
                                        '-range' => '',
                                        '-class' => 'constant',
                                        '-left' => '',
                                        '-val' => 'ADDRWIDTH'
                                      },
                       'textio' => {},
                       'integer' => {
                                      '-size' => '',
                                      '-type' => '',
                                      '-init' => '',
                                      '-port' => '',
                                      '-name' => 'INTEGER',
                                      '-range' => '',
                                      '-class' => '',
                                      '-val' => 'INTEGER'
                                    },
                       'databus' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'databus',
                                      '-range' => '[DATAWIDTH - 1:0]',
                                      '-class' => 'port',
                                      '-left' => 'DATAWIDTH - 1',
                                      '-val' => 'databus'
                                    },
                       'std_logic_1164' => {},
                       'addrbus' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'addrbus',
                                      '-range' => '[ADDRWIDTH - 1:0]',
                                      '-class' => 'port',
                                      '-left' => 'ADDRWIDTH - 1',
                                      '-val' => 'addrbus'
                                    },
                       'internal_program_memory' => {
                                                      '-size' => '',
                                                      '-type' => '',
                                                      '-init' => '',
                                                      '-port' => '',
                                                      '-name' => 'INTERNAL_PROGRAM_MEMORY',
                                                      '-range' => '',
                                                      '-class' => '',
                                                      '-val' => 'INTERNAL_PROGRAM_MEMORY'
                                                    },
                       'rd' => {
                                 '-size' => '',
                                 '-type' => 'std_logic',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '',
                                 '-name' => 'rd',
                                 '-range' => '',
                                 '-class' => 'port',
                                 '-left' => '',
                                 '-val' => 'rd'
                               },
                       'std_logic_vector' => {},
                       'ieee' => {},
                       'datawidth' => {
                                        '-size' => '',
                                        '-type' => 'integer',
                                        '-init' => '8',
                                        '-port' => '',
                                        '-right' => '',
                                        '-name' => 'DATAWIDTH',
                                        '-range' => '',
                                        '-class' => 'constant',
                                        '-left' => '',
                                        '-val' => 'DATAWIDTH'
                                      },
                       'std' => {}
                     }
        };