internal_data_memory.symb

USB v1.1 RTL and design specification

$VAR1 = {
          '-main' => {
                       'std_logic' => {},
                       'addrwidth' => {
                                        '-size' => '',
                                        '-type' => 'integer',
                                        '-init' => '8',
                                        '-port' => '',
                                        '-right' => '',
                                        '-name' => 'ADDRWIDTH',
                                        '-range' => '',
                                        '-class' => 'constant',
                                        '-left' => '',
                                        '-val' => 'ADDRWIDTH'
                                      },
                       'integer' => {
                                      '-size' => '',
                                      '-type' => '',
                                      '-init' => '',
                                      '-port' => '',
                                      '-name' => 'INTEGER',
                                      '-range' => '',
                                      '-class' => '',
                                      '-val' => 'INTEGER'
                                    },
                       'databusi' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'databusi',
                                       '-range' => '[DATAWIDTH - 1:0]',
                                       '-class' => 'port',
                                       '-left' => 'DATAWIDTH - 1',
                                       '-val' => 'databusi'
                                     },
                       'std_logic_1164' => {},
                       'addrbus' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'addrbus',
                                      '-range' => '[ADDRWIDTH - 1:0]',
                                      '-class' => 'port',
                                      '-left' => 'ADDRWIDTH - 1',
                                      '-val' => 'addrbus'
                                    },
                       'wr' => {
                                 '-size' => '',
                                 '-type' => 'std_logic',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '',
                                 '-name' => 'wr',
                                 '-range' => '',
                                 '-class' => 'port',
                                 '-left' => '',
                                 '-val' => 'wr'
                               },
                       'databuso' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'databuso',
                                       '-range' => '[DATAWIDTH - 1:0]',
                                       '-class' => 'port',
                                       '-left' => 'DATAWIDTH - 1',
                                       '-val' => 'databuso'
                                     },
                       'internal_data_memory' => {
                                                   '-size' => '',
                                                   '-type' => '',
                                                   '-init' => '',
                                                   '-port' => '',
                                                   '-name' => 'INTERNAL_DATA_MEMORY',
                                                   '-range' => '',
                                                   '-class' => '',
                                                   '-val' => 'INTERNAL_DATA_MEMORY'
                                                 },
                       'ieee' => {},
                       'datawidth' => {
                                        '-size' => '',
                                        '-type' => 'integer',
                                        '-init' => '8',
                                        '-port' => '',
                                        '-right' => '',
                                        '-name' => 'DATAWIDTH',
                                        '-range' => '',
                                        '-class' => 'constant',
                                        '-left' => '',
                                        '-val' => 'DATAWIDTH'
                                      },
                       'std_logic_vector' => {},
                       'rd' => {
                                 '-size' => '',
                                 '-type' => 'std_logic',
                                 '-init' => '',
                                 '-port' => '',
                                 '-right' => '',
                                 '-name' => 'rd',
                                 '-range' => '',
                                 '-class' => 'port',
                                 '-left' => '',
                                 '-val' => 'rd'
                               }
                     }
        };