⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 special_function_register.symb

📁 USB v1.1 RTL and design specification
💻 SYMB
字号:
$VAR1 = {
          '-main' => {
                       'sfroe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'sfroe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'sfroe'
                                  },
                       'std_logic' => {},
                       'sfrwe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'sfrwe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'sfrwe'
                                  },
                       'sfr_rv' => {
                                     '-size' => '',
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b11111111',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'SFR_RV',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => 'SFR_RV'
                                   },
                       'sfraddr' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'sfraddr',
                                      '-range' => '[6:0]',
                                      '-class' => 'port',
                                      '-left' => '6',
                                      '-val' => 'sfraddr'
                                    },
                       'std_logic_1164' => {},
                       'clk' => {
                                  '-size' => '',
                                  '-type' => 'std_logic',
                                  '-init' => '',
                                  '-port' => '',
                                  '-right' => '',
                                  '-name' => 'clk',
                                  '-range' => '',
                                  '-class' => 'port',
                                  '-left' => '',
                                  '-val' => 'clk'
                                },
                       'reset' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'reset',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'reset'
                                  },
                       'sfrdatai' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'sfrdatai',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'sfrdatai'
                                     },
                       'sfrdatao' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'sfrdatao',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'sfrdatao'
                                     },
                       'ieee' => {},
                       'special_function_register' => {
                                                        '-size' => '',
                                                        '-type' => '',
                                                        '-init' => '',
                                                        '-port' => '',
                                                        '-name' => 'SPECIAL_FUNCTION_REGISTER',
                                                        '-range' => '',
                                                        '-class' => '',
                                                        '-val' => 'SPECIAL_FUNCTION_REGISTER'
                                                      },
                       'sfr_id' => {
                                     '-size' => '',
                                     '-type' => 'std_logic_vector',
                                     '-init' => '7\'b1111111',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'SFR_ID',
                                     '-range' => '[6:0]',
                                     '-class' => 'constant',
                                     '-left' => '6',
                                     '-val' => 'SFR_ID'
                                   },
                       'std_logic_vector' => {
                                               '-size' => '',
                                               '-type' => '',
                                               '-init' => '',
                                               '-port' => '',
                                               '-name' => 'STD_LOGIC_VECTOR',
                                               '-range' => '',
                                               '-class' => '',
                                               '-val' => 'STD_LOGIC_VECTOR'
                                             }
                     }
        };

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -