utility.symb

USB v1.1 RTL and design specification

                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11101010',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_A_R2',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_A_R2'
                                     },
                       'ajmp_4' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b10000001',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'AJMP_4',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`AJMP_4'
                                   },
                       'anl_a_r5' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01011101',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ANL_A_R5',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ANL_A_R5'
                                     },
                       'mov_a_r3' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11101011',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_A_R3',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_A_R3'
                                     },
                       'ajmp_5' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b10100001',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'AJMP_5',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`AJMP_5'
                                   },
                       'anl_a_r6' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01011110',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ANL_A_R6',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ANL_A_R6'
                                     },
                       'mov_a_r4' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11101100',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_A_R4',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_A_R4'
                                     },
                       'ajmp_6' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b11000001',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'AJMP_6',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`AJMP_6'
                                   },
                       'anl_a_r7' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01011111',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ANL_A_R7',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ANL_A_R7'
                                     },
                       'mov_a_r5' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11101101',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_A_R5',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_A_R5'
                                     },
                       'ajmp_7' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b11100001',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'AJMP_7',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`AJMP_7'
                                   },
                       'mov_a_r6' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11101110',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_A_R6',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_A_R6'
                                     },
                       'mov_a_r7' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11101111',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_A_R7',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_A_R7'
                                     },
                       'cjne_r0_n' => {
                                        '-size' => 8,
                                        '-type' => 'std_logic_vector',
                                        '-init' => '8\'b10111000',
                                        '-port' => '',
                                        '-right' => '0',
                                        '-name' => 'CJNE_R0_N',
                                        '-range' => '[7:0]',
                                        '-class' => 'constant',
                                        '-left' => '7',
                                        '-val' => '`CJNE_R0_N'
                                      },
                       'orl_a_r0' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01001000',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ORL_A_R0',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ORL_A_R0'
                                     },
                       'orl_a_r1' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01001001',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ORL_A_R1',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ORL_A_R1'
                                     },
                       'orl_a_r2' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01001010',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ORL_A_R2',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ORL_A_R2'
                                     },
                       'mov_bit_c' => {
                                        '-size' => 8,
                                        '-type' => 'std_logic_vector',
                                        '-init' => '8\'b10010010',
                                        '-port' => '',
                                        '-right' => '0',
                                        '-name' => 'MOV_BIT_C',
                                        '-range' => '[7:0]',
                                        '-class' => 'constant',
                                        '-left' => '7',
                                        '-val' => '`MOV_BIT_C'
                                      },
                       'orl_a_r3' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01001011',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ORL_A_R3',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ORL_A_R3'
                                     },
                       'orl_a_r4' => {