utility.symb

USB v1.1 RTL and design specification

                                     '-right' => '0',
                                     '-name' => 'TH1_RV',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`TH1_RV'
                                   },
                       'mov_r1_addr' => {
                                          '-size' => 8,
                                          '-type' => 'std_logic_vector',
                                          '-init' => '8\'b10101001',
                                          '-port' => '',
                                          '-right' => '0',
                                          '-name' => 'MOV_R1_ADDR',
                                          '-range' => '[7:0]',
                                          '-class' => 'constant',
                                          '-left' => '7',
                                          '-val' => '`MOV_R1_ADDR'
                                        },
                       'xrl_a_r0' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101000',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R0',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R0'
                                     },
                       'xrl_a_r1' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101001',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R1',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R1'
                                     },
                       'xrl_a_r2' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101010',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R2',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R2'
                                     },
                       'ip_id' => {
                                    '-size' => 7,
                                    '-type' => 'std_logic_vector',
                                    '-init' => '7\'b0111000',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'IP_ID',
                                    '-range' => '[6:0]',
                                    '-class' => 'constant',
                                    '-left' => '6',
                                    '-val' => '`IP_ID'
                                  },
                       'xrl_a_r3' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101011',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R3',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R3'
                                     },
                       'xrl_a_r4' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101100',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R4',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R4'
                                     },
                       'xrl_a_r5' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101101',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R5',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R5'
                                     },
                       'xrl_a_r6' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101110',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R6',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R6'
                                     },
                       'movc_a_pc' => {
                                        '-size' => 8,
                                        '-type' => 'std_logic_vector',
                                        '-init' => '8\'b10000011',
                                        '-port' => '',
                                        '-right' => '0',
                                        '-name' => 'MOVC_A_PC',
                                        '-range' => '[7:0]',
                                        '-class' => 'constant',
                                        '-left' => '7',
                                        '-val' => '`MOVC_A_PC'
                                      },
                       'xrl_a_r7' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01101111',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'XRL_A_R7',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`XRL_A_R7'
                                     },
                       'reti' => {
                                   '-size' => 8,
                                   '-type' => 'std_logic_vector',
                                   '-init' => '8\'b00110010',
                                   '-port' => '',
                                   '-right' => '0',
                                   '-name' => 'RETI',
                                   '-range' => '[7:0]',
                                   '-class' => 'constant',
                                   '-left' => '7',
                                   '-val' => '`RETI'
                                 },
                       'mul_ab' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b10100100',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'MUL_AB',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`MUL_AB'
                                   },
                       'cpl_a' => {
                                    '-size' => 8,
                                    '-type' => 'std_logic_vector',
                                    '-init' => '8\'b11110100',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'CPL_A',
                                    '-range' => '[7:0]',
                                    '-class' => 'constant',
                                    '-left' => '7',
                                    '-val' => '`CPL_A'
                                  },
                       'orl_c_nbit' => {
                                         '-size' => 8,
                                         '-type' => 'std_logic_vector',
                                         '-init' => '8\'b10100000',
                                         '-port' => '',
                                         '-right' => '0',
                                         '-name' => 'ORL_C_NBIT',
                                         '-range' => '[7:0]',
                                         '-class' => 'constant',
                                         '-left' => '7',
                                         '-val' => '`ORL_C_NBIT'
                                       },
                       'mov_ir1_a' => {
                                        '-size' => 8,
                                        '-type' => 'std_logic_vector',
                                        '-init' => '8\'b11110111',
                                        '-port' => '',
                                        '-right' => '0',
                                        '-name' => 'MOV_IR1_A',
                                        '-range' => '[7:0]',
                                        '-class' => 'constant',
                                        '-left' => '7',
                                        '-val' => '`MOV_IR1_A'
                                      },
                       'cpl_c' => {
                                    '-size' => 8,
                                    '-type' => 'std_logic_vector',
                                    '-init' => '8\'b10110011',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'CPL_C',
                                    '-range' => '[7:0]',
                                    '-class' => 'constant',
                                    '-left' => '7',
                                    '-val' => '`CPL_C'
                                  },
                       'mov_r0_addr' => {
                                          '-size' => 8,
                                          '-type' => 'std_logic_vector',
                                          '-init' => '8\'b10101000',
                                          '-port' => '',
                                          '-right' => '0',
                                          '-name' => 'MOV_R0_ADDR',
                                          '-range' => '[7:0]',
                                          '-class' => 'constant',
                                          '-left' => '7',
                                          '-val' => '`MOV_R0_ADDR'
                                        },
                       'mov_addr_a' => {
                                         '-size' => 8,
                                         '-type' => 'std_logic_vector',
                                         '-init' => '8\'b11110101',
                                         '-port' => '',
                                         '-right' => '0',
                                         '-name' => 'MOV_ADDR_A',
                                         '-range' => '[7:0]',
                                         '-class' => 'constant',