utility.symb

USB v1.1 RTL and design specification

                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b11000100',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'SWAP_A',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`SWAP_A'
                                   },
                       'addc_r7' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111111',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R7',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R7'
                                    },
                       'acc_rv' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00000000',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'ACC_RV',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`ACC_RV'
                                   },
                       'addc_ir0' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b00110110',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ADDC_IR0',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ADDC_IR0'
                                     },
                       'addc_ir1' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b00110111',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ADDC_IR1',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`ADDC_IR1'
                                     },
                       'subb_addr' => {
                                        '-size' => 8,
                                        '-type' => 'std_logic_vector',
                                        '-init' => '8\'b10010101',
                                        '-port' => '',
                                        '-right' => '0',
                                        '-name' => 'SUBB_ADDR',
                                        '-range' => '[7:0]',
                                        '-class' => 'constant',
                                        '-left' => '7',
                                        '-val' => '`SUBB_ADDR'
                                      },
                       'p0_id' => {
                                    '-size' => 7,
                                    '-type' => 'std_logic_vector',
                                    '-init' => '7\'b0000000',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'P0_ID',
                                    '-range' => '[6:0]',
                                    '-class' => 'constant',
                                    '-left' => '6',
                                    '-val' => '`P0_ID'
                                  },
                       'dph_rv' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00000000',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DPH_RV',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DPH_RV'
                                   },
                       'mov_r2_addr' => {
                                          '-size' => 8,
                                          '-type' => 'std_logic_vector',
                                          '-init' => '8\'b10101010',
                                          '-port' => '',
                                          '-right' => '0',
                                          '-name' => 'MOV_R2_ADDR',
                                          '-range' => '[7:0]',
                                          '-class' => 'constant',
                                          '-left' => '7',
                                          '-val' => '`MOV_R2_ADDR'
                                        },
                       'std_logic_1164' => {},
                       'mov_r3_n' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b01111011',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_R3_N',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_R3_N'
                                     },
                       'rl_a' => {
                                   '-size' => 8,
                                   '-type' => 'std_logic_vector',
                                   '-init' => '8\'b00100011',
                                   '-port' => '',
                                   '-right' => '0',
                                   '-name' => 'RL_A',
                                   '-range' => '[7:0]',
                                   '-class' => 'constant',
                                   '-left' => '7',
                                   '-val' => '`RL_A'
                                 },
                       'p1_rv' => {
                                    '-size' => 8,
                                    '-type' => 'std_logic_vector',
                                    '-init' => '8\'b11111111',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'P1_RV',
                                    '-range' => '[7:0]',
                                    '-class' => 'constant',
                                    '-left' => '7',
                                    '-val' => '`P1_RV'
                                  },
                       'movc_a_dptr' => {
                                          '-size' => 8,
                                          '-type' => 'std_logic_vector',
                                          '-init' => '8\'b10010011',
                                          '-port' => '',
                                          '-right' => '0',
                                          '-name' => 'MOVC_A_DPTR',
                                          '-range' => '[7:0]',
                                          '-class' => 'constant',
                                          '-left' => '7',
                                          '-val' => '`MOVC_A_DPTR'
                                        },
                       'jnz' => {
                                  '-size' => 8,
                                  '-type' => 'std_logic_vector',
                                  '-init' => '8\'b01110000',
                                  '-port' => '',
                                  '-right' => '0',
                                  '-name' => 'JNZ',
                                  '-range' => '[7:0]',
                                  '-class' => 'constant',
                                  '-left' => '7',
                                  '-val' => '`JNZ'
                                },
                       'sbuf_rv' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00000000',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'SBUF_RV',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`SBUF_RV'
                                    },
                       'th0_id' => {
                                     '-size' => 7,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '7\'b0001100',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'TH0_ID',
                                     '-range' => '[6:0]',
                                     '-class' => 'constant',
                                     '-left' => '6',
                                     '-val' => '`TH0_ID'
                                   },
                       'b_id' => {
                                   '-size' => 7,
                                   '-type' => 'std_logic_vector',
                                   '-init' => '7\'b1110000',
                                   '-port' => '',
                                   '-right' => '0',
                                   '-name' => 'B_ID',
                                   '-range' => '[6:0]',
                                   '-class' => 'constant',
                                   '-left' => '6',
                                   '-val' => '`B_ID'
                                 },
                       'psw_rv' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00000000',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'PSW_RV',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`PSW_RV'
                                   },
                       'sp_rv' => {
                                    '-size' => 8,
                                    '-type' => 'std_logic_vector',
                                    '-init' => '8\'b00000111',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'SP_RV',
                                    '-range' => '[7:0]',
                                    '-class' => 'constant',
                                    '-left' => '7',
                                    '-val' => '`SP_RV'
                                  },
                       'th1_rv' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00000000',
                                     '-port' => '',