utility.symb

USB v1.1 RTL and design specification

$VAR1 = {
          '-main' => {
                       'dec_r1' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011001',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R1',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R1'
                                   },
                       'sjmp' => {
                                   '-size' => 8,
                                   '-type' => 'std_logic_vector',
                                   '-init' => '8\'b10000000',
                                   '-port' => '',
                                   '-right' => '0',
                                   '-name' => 'SJMP',
                                   '-range' => '[7:0]',
                                   '-class' => 'constant',
                                   '-left' => '7',
                                   '-val' => '`SJMP'
                                 },
                       'dec_r2' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011010',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R2',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R2'
                                   },
                       'dec_r3' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011011',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R3',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R3'
                                   },
                       'dec_r4' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011100',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R4',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R4'
                                   },
                       'addc_r0' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111000',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R0',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R0'
                                    },
                       'dec_r5' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011101',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R5',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R5'
                                   },
                       'addc_r1' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111001',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R1',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R1'
                                    },
                       'dec_r6' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011110',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R6',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R6'
                                   },
                       'jnc' => {
                                  '-size' => 8,
                                  '-type' => 'std_logic_vector',
                                  '-init' => '8\'b01010000',
                                  '-port' => '',
                                  '-right' => '0',
                                  '-name' => 'JNC',
                                  '-range' => '[7:0]',
                                  '-class' => 'constant',
                                  '-left' => '7',
                                  '-val' => '`JNC'
                                },
                       'addc_r2' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111010',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R2',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R2'
                                    },
                       'dec_r7' => {
                                     '-size' => 8,
                                     '-type' => 'std_logic_vector',
                                     '-init' => '8\'b00011111',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'DEC_R7',
                                     '-range' => '[7:0]',
                                     '-class' => 'constant',
                                     '-left' => '7',
                                     '-val' => '`DEC_R7'
                                   },
                       'addc_r3' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111011',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R3',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R3'
                                    },
                       'mov_r3_a' => {
                                       '-size' => 8,
                                       '-type' => 'std_logic_vector',
                                       '-init' => '8\'b11111011',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'MOV_R3_A',
                                       '-range' => '[7:0]',
                                       '-class' => 'constant',
                                       '-left' => '7',
                                       '-val' => '`MOV_R3_A'
                                     },
                       'addc_r4' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111100',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R4',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R4'
                                    },
                       'addc_r5' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111101',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R5',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R5'
                                    },
                       'movx_a_ir0' => {
                                         '-size' => 8,
                                         '-type' => 'std_logic_vector',
                                         '-init' => '8\'b11100010',
                                         '-port' => '',
                                         '-right' => '0',
                                         '-name' => 'MOVX_A_IR0',
                                         '-range' => '[7:0]',
                                         '-class' => 'constant',
                                         '-left' => '7',
                                         '-val' => '`MOVX_A_IR0'
                                       },
                       'addc_r6' => {
                                      '-size' => 8,
                                      '-type' => 'std_logic_vector',
                                      '-init' => '8\'b00111110',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ADDC_R6',
                                      '-range' => '[7:0]',
                                      '-class' => 'constant',
                                      '-left' => '7',
                                      '-val' => '`ADDC_R6'
                                    },
                       'movx_a_ir1' => {
                                         '-size' => 8,
                                         '-type' => 'std_logic_vector',
                                         '-init' => '8\'b11100011',
                                         '-port' => '',
                                         '-right' => '0',
                                         '-name' => 'MOVX_A_IR1',
                                         '-range' => '[7:0]',
                                         '-class' => 'constant',
                                         '-left' => '7',
                                         '-val' => '`MOVX_A_IR1'
                                       },
                       'swap_a' => {
                                     '-size' => 8,