chip_oci.symb

USB v1.1 RTL and design specification

$VAR1 = {
          '-main' => {
                       'sfroe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'sfroe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'sfroe'
                                  },
                       'std_logic' => {},
                       'debugack' => {
                                       '-size' => '',
                                       '-type' => 'std_logic',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '',
                                       '-name' => 'debugack',
                                       '-range' => '',
                                       '-class' => 'port',
                                       '-left' => '',
                                       '-val' => 'debugack'
                                     },
                       'textio' => {},
                       'sfraddr' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'sfraddr',
                                      '-range' => '[6:0]',
                                      '-class' => 'port',
                                      '-left' => '6',
                                      '-val' => 'sfraddr'
                                    },
                       'ramdatao' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ramdatao',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'ramdatao'
                                     },
                       'ramaddr' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'ramaddr',
                                      '-range' => '[7:0]',
                                      '-class' => 'port',
                                      '-left' => '7',
                                      '-val' => 'ramaddr'
                                    },
                       'sfrdatai' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'sfrdatai',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'sfrdatai'
                                     },
                       'chip_oci' => {
                                       '-size' => '',
                                       '-type' => '',
                                       '-init' => '',
                                       '-port' => '',
                                       '-name' => 'CHIP_OCI',
                                       '-range' => '',
                                       '-class' => '',
                                       '-val' => 'CHIP_OCI'
                                     },
                       'ramwe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'ramwe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'ramwe'
                                  },
                       'flush' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'flush',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'flush'
                                  },
                       'fetch' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'fetch',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'fetch'
                                  },
                       'sfrdatao' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'sfrdatao',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'sfrdatao'
                                     },
                       'ieee' => {},
                       'std_logic_vector' => {},
                       'std' => {},
                       'sfrwe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'sfrwe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'sfrwe'
                                  },
                       'romoe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'romoe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'romoe'
                                  },
                       'debugprog' => {
                                        '-size' => '',
                                        '-type' => 'std_logic',
                                        '-init' => '',
                                        '-port' => '',
                                        '-right' => '',
                                        '-name' => 'debugprog',
                                        '-range' => '',
                                        '-class' => 'port',
                                        '-left' => '',
                                        '-val' => 'debugprog'
                                      },
                       'std_logic_1164' => {},
                       'databusi' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'databusi',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'databusi'
                                     },
                       'clk' => {
                                  '-size' => '',
                                  '-type' => 'std_logic',
                                  '-init' => '',
                                  '-port' => '',
                                  '-right' => '',
                                  '-name' => 'clk',
                                  '-range' => '',
                                  '-class' => 'port',
                                  '-left' => '',
                                  '-val' => 'clk'
                                },
                       'addrbus' => {
                                      '-size' => '',
                                      '-type' => 'std_logic_vector',
                                      '-init' => '',
                                      '-port' => '',
                                      '-right' => '0',
                                      '-name' => 'addrbus',
                                      '-range' => '[13:0]',
                                      '-class' => 'port',
                                      '-left' => '13',
                                      '-val' => 'addrbus'
                                    },
                       'ramoe' => {
                                    '-size' => '',
                                    '-type' => 'std_logic',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'ramoe',
                                    '-range' => '',
                                    '-class' => 'port',
                                    '-left' => '',
                                    '-val' => 'ramoe'
                                  },
                       'rst' => {
                                  '-size' => '',
                                  '-type' => 'std_logic',
                                  '-init' => '',
                                  '-port' => '',
                                  '-right' => '',
                                  '-name' => 'rst',
                                  '-range' => '',
                                  '-class' => 'port',
                                  '-left' => '',
                                  '-val' => 'rst'
                                },
                       'debugstep' => {
                                        '-size' => '',
                                        '-type' => 'std_logic',
                                        '-init' => '',
                                        '-port' => '',
                                        '-right' => '',
                                        '-name' => 'debugstep',
                                        '-range' => '',
                                        '-class' => 'port',
                                        '-left' => '',
                                        '-val' => 'debugstep'
                                      },
                       'accreg' => {
                                     '-size' => '',
                                     '-type' => 'std_logic_vector',
                                     '-init' => '',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'accreg',
                                     '-range' => '[7:0]',
                                     '-class' => 'port',
                                     '-left' => '7',
                                     '-val' => 'accreg'
                                   },
                       'ramdatai' => {
                                       '-size' => '',
                                       '-type' => 'std_logic_vector',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '0',
                                       '-name' => 'ramdatai',
                                       '-range' => '[7:0]',
                                       '-class' => 'port',
                                       '-left' => '7',
                                       '-val' => 'ramdatai'
                                     },
                       'debugreq' => {
                                       '-size' => '',
                                       '-type' => 'std_logic',
                                       '-init' => '',
                                       '-port' => '',
                                       '-right' => '',
                                       '-name' => 'debugreq',
                                       '-range' => '',
                                       '-class' => 'port',
                                       '-left' => '',
                                       '-val' => 'debugreq'
                                     }
                     }
        };