internal_data_memory.code

USB v1.1 RTL and design specification

$VAR1 = {
          '-flags' => {
                        'defines_included' => undef
                      },
          '-inits' => undef,
          '-design_name' => 'INTERNAL_DATA_MEMORY',
          '-code' => '//*******************************************************************--
// Copyright (c) 1999-2001  Evatronix SA                             --
//*******************************************************************--
// Please review the terms of the license agreement before using     --
// this file. If you are not an authorized user, please destroy this --
// source code file and notify Evatronix SA immediately that you     --
// inadvertently received an unauthorized copy.                      --
//*******************************************************************--
//---------------------------------------------------------------------
// Project name         : C8051
// Project description  : C8051 Microcontroller Unit
//
// File name            : CHIPRAM.VHD
// File contents        : Entity INTERNAL_DATA_MEMORY
//                        Architecture SIM of INTERNAL_DATA_MEMORY
// Purpose              : Asynchronous Data Memory
//                        Dual Data port
//                        Single Address port
//
// Destination library  : C8051_LIB
// Dependencies         : IEEE.STD_LOGIC_1164
//
// Design Engineer      : M.B.
// Quality Engineer     : M.B.
// Version              : 3.01
// Last modification    : 2001-10-01
//---------------------------------------------------------------------
module INTERNAL_DATA_MEMORY (addrbus, rd, wr, databusi, databuso);

鴓arameter DATAWIDTH  = 8;
parameter ADDRWIDTH  = 8;
input[ADDRWIDTH - 1:0] addrbus; 
input rd; 
input wr; 
input[DATAWIDTH - 1:0] databusi; 
output[DATAWIDTH - 1:0] databuso; 
wire[DATAWIDTH - 1:0] databuso;

'
        };