internal_open_drain.symb

USB v1.1 RTL and design specification

$VAR1 = {
          '-main' => {
                       'integer' => {
                                      '-size' => '',
                                      '-type' => '',
                                      '-init' => '',
                                      '-port' => '',
                                      '-name' => 'INTEGER',
                                      '-range' => '',
                                      '-class' => '',
                                      '-val' => 'INTEGER'
                                    },
                       'input' => {
                                    '-size' => '',
                                    '-type' => 'std_logic_vector',
                                    '-init' => '',
                                    '-port' => '',
                                    '-right' => '0',
                                    '-name' => 'input',
                                    '-range' => '[WIDTH - 1:0]',
                                    '-class' => 'port',
                                    '-left' => 'WIDTH - 1',
                                    '-val' => 'input_xhdl0'
                                  },
                       'width' => {
                                    '-size' => '',
                                    '-type' => 'integer',
                                    '-init' => '8',
                                    '-port' => '',
                                    '-right' => '',
                                    '-name' => 'WIDTH',
                                    '-range' => '',
                                    '-class' => 'constant',
                                    '-left' => '',
                                    '-val' => 'WIDTH'
                                  },
                       'std_logic_1164' => {},
                       'output' => {
                                     '-size' => '',
                                     '-type' => 'std_logic_vector',
                                     '-init' => '',
                                     '-port' => '',
                                     '-right' => '0',
                                     '-name' => 'output',
                                     '-range' => '[WIDTH - 1:0]',
                                     '-class' => 'port',
                                     '-left' => 'WIDTH - 1',
                                     '-val' => 'output_xhdl1'
                                   },
                       'std_logic_vector' => {},
                       'internal_open_drain' => {
                                                  '-size' => '',
                                                  '-type' => '',
                                                  '-init' => '',
                                                  '-port' => '',
                                                  '-name' => 'INTERNAL_OPEN_DRAIN',
                                                  '-range' => '',
                                                  '-class' => '',
                                                  '-val' => 'INTERNAL_OPEN_DRAIN'
                                                },
                       'ieee' => {}
                     }
        };