jtdkz.tan.qmsg

这是交通灯控制器的设计系统,里面有文字说明以及详细的图形,希望大家喜欢

{ "Info" "ITDB_TH_RESULT" "ztj:u1\|state.d rst1 clk1 0.500 ns register " "Info: th for register \"ztj:u1\|state.d\" (data pin = \"rst1\", clock pin = \"clk1\") is 0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk1 1 CLK PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ztj:u1\|state.d 2 REG LC2_E36 4 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_E36; Fanout = 4; REG Node = 'ztj:u1\|state.d'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk1 ztj:u1|state.d } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|state.d } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|state.d } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns rst1 1 PIN PIN_54 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 17; PIN Node = 'rst1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 3.200 ns ztj:u1\|state.d 2 REG LC2_E36 4 " "Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC2_E36; Fanout = 4; REG Node = 'ztj:u1\|state.d'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { rst1 ztj:u1|state.d } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 93.75 % ) " "Info: Total cell delay = 3.000 ns ( 93.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 6.25 % ) " "Info: Total interconnect delay = 0.200 ns ( 6.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { rst1 ztj:u1|state.d } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { rst1 rst1~out ztj:u1|state.d } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|state.d } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|state.d } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { rst1 ztj:u1|state.d } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "3.200 ns" { rst1 rst1~out ztj:u1|state.d } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 15 17:51:23 2007 " "Info: Processing ended: Sun Jul 15 17:51:23 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}