decl7s.vhd

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library ieee;
use ieee.std_logic_1164.all;
entity decl7s is
port(numi:in integer range 0 to 9;
     numo:out std_logic_vector(6 downto 0) );
end;
architecture one of decl7s is
begin
process(numi)
begin
case numi is
when 0 => numo <= "0111111";
when 1 => numo <= "0000110";
when 2 => numo <= "1011011";
when 3 => numo <= "1001111";
when 4 => numo <= "1100110";
when 5 => numo <= "1101101";
when 6 => numo <= "1111101";
when 7 => numo <= "0000111";
when 8 => numo <= "1111111";
when 9 => numo <= "1101111";
when others => null;
end case;
end process;
end;