jtdkz.tan.qmsg

这是交通灯控制器的设计系统,里面有文字说明以及详细的图形,希望大家喜欢

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } } { "g:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register ztj:u1\|\\cnt:en register ztj:u1\|\\cnt:en 64.1 MHz 15.6 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 64.1 MHz between source register \"ztj:u1\|\\cnt:en\" and destination register \"ztj:u1\|\\cnt:en\" (period= 15.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest register register " "Info: + Longest register to register delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ztj:u1\|\\cnt:en 1 REG LC1_E36 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1\|\\cnt:en'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ztj:u1|\cnt:en } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.700 ns) 1.700 ns ztj:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC3_E34 2 " "Info: 2: + IC(1.000 ns) + CELL(0.700 ns) = 1.700 ns; Loc. = LC3_E34; Fanout = 2; COMB Node = 'ztj:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ztj:u1|\cnt:en ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "g:/quartus/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 3.100 ns ztj:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\] 3 COMB LC4_E34 2 " "Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 3.100 ns; Loc. = LC4_E34; Fanout = 2; COMB Node = 'ztj:u1\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "g:/quartus/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 5.600 ns ztj:u1\|Equal2~38 4 COMB LC4_E35 2 " "Info: 4: + IC(0.900 ns) + CELL(1.600 ns) = 5.600 ns; Loc. = LC4_E35; Fanout = 2; COMB Node = 'ztj:u1\|Equal2~38'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ztj:u1|Equal2~38 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 7.300 ns ztj:u1\|Equal2~39 5 COMB LC5_E35 2 " "Info: 5: + IC(0.300 ns) + CELL(1.400 ns) = 7.300 ns; Loc. = LC5_E35; Fanout = 2; COMB Node = 'ztj:u1\|Equal2~39'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ztj:u1|Equal2~38 ztj:u1|Equal2~39 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 9.000 ns ztj:u1\|Equal2~40 6 COMB LC1_E35 4 " "Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 9.000 ns; Loc. = LC1_E35; Fanout = 4; COMB Node = 'ztj:u1\|Equal2~40'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ztj:u1|Equal2~39 ztj:u1|Equal2~40 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.600 ns) 11.500 ns ztj:u1\|Selector4~222 7 COMB LC6_E36 1 " "Info: 7: + IC(0.900 ns) + CELL(1.600 ns) = 11.500 ns; Loc. = LC6_E36; Fanout = 1; COMB Node = 'ztj:u1\|Selector4~222'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { ztj:u1|Equal2~40 ztj:u1|Selector4~222 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 13.200 ns ztj:u1\|Selector4~223 8 COMB LC8_E36 1 " "Info: 8: + IC(0.300 ns) + CELL(1.400 ns) = 13.200 ns; Loc. = LC8_E36; Fanout = 1; COMB Node = 'ztj:u1\|Selector4~223'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { ztj:u1|Selector4~222 ztj:u1|Selector4~223 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 14.500 ns ztj:u1\|\\cnt:en 9 REG LC1_E36 14 " "Info: 9: + IC(0.300 ns) + CELL(1.000 ns) = 14.500 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1\|\\cnt:en'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { ztj:u1|Selector4~223 ztj:u1|\cnt:en } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.500 ns ( 72.41 % ) " "Info: Total cell delay = 10.500 ns ( 72.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 27.59 % ) " "Info: Total interconnect delay = 4.000 ns ( 27.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { ztj:u1|\cnt:en ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ztj:u1|Equal2~38 ztj:u1|Equal2~39 ztj:u1|Equal2~40 ztj:u1|Selector4~222 ztj:u1|Selector4~223 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { ztj:u1|\cnt:en ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ztj:u1|Equal2~38 ztj:u1|Equal2~39 ztj:u1|Equal2~40 ztj:u1|Selector4~222 ztj:u1|Selector4~223 ztj:u1|\cnt:en } { 0.000ns 1.000ns 0.000ns 0.900ns 0.300ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 0.700ns 1.400ns 1.600ns 1.400ns 1.400ns 1.600ns 1.400ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk1 1 CLK PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ztj:u1\|\\cnt:en 2 REG LC1_E36 14 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1\|\\cnt:en'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk1 1 CLK PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ztj:u1\|\\cnt:en 2 REG LC1_E36 14 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1\|\\cnt:en'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { ztj:u1|\cnt:en ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ztj:u1|Equal2~38 ztj:u1|Equal2~39 ztj:u1|Equal2~40 ztj:u1|Selector4~222 ztj:u1|Selector4~223 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { ztj:u1|\cnt:en ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ztj:u1|Equal2~38 ztj:u1|Equal2~39 ztj:u1|Equal2~40 ztj:u1|Selector4~222 ztj:u1|Selector4~223 ztj:u1|\cnt:en } { 0.000ns 1.000ns 0.000ns 0.900ns 0.300ns 0.300ns 0.900ns 0.300ns 0.300ns } { 0.000ns 0.700ns 1.400ns 1.600ns 1.400ns 1.400ns 1.600ns 1.400ns 1.000ns } "" } } { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ztj:u1\|\\cnt:en agt1 clk1 13.000 ns register " "Info: tsu for register \"ztj:u1\|\\cnt:en\" (data pin = \"agt1\", clock pin = \"clk1\") is 13.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Longest pin register " "Info: + Longest pin to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns agt1 1 PIN PIN_10 2 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_10; Fanout = 2; PIN Node = 'agt1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { agt1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.600 ns) 9.800 ns ztj:u1\|numo\[5\]~167 2 COMB LC5_E31 7 " "Info: 2: + IC(3.300 ns) + CELL(1.600 ns) = 9.800 ns; Loc. = LC5_E31; Fanout = 7; COMB Node = 'ztj:u1\|numo\[5\]~167'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { agt1 ztj:u1|numo[5]~167 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.400 ns) 12.500 ns ztj:u1\|numo\[3\]~174 3 COMB LC3_E32 7 " "Info: 3: + IC(1.300 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC3_E32; Fanout = 7; COMB Node = 'ztj:u1\|numo\[3\]~174'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { ztj:u1|numo[5]~167 ztj:u1|numo[3]~174 } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.000 ns) 14.800 ns ztj:u1\|\\cnt:en 4 REG LC1_E36 14 " "Info: 4: + IC(1.300 ns) + CELL(1.000 ns) = 14.800 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1\|\\cnt:en'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { ztj:u1|numo[3]~174 ztj:u1|\cnt:en } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.900 ns ( 60.14 % ) " "Info: Total cell delay = 8.900 ns ( 60.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.900 ns ( 39.86 % ) " "Info: Total interconnect delay = 5.900 ns ( 39.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { agt1 ztj:u1|numo[5]~167 ztj:u1|numo[3]~174 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { agt1 agt1~out ztj:u1|numo[5]~167 ztj:u1|numo[3]~174 ztj:u1|\cnt:en } { 0.000ns 0.000ns 3.300ns 1.300ns 1.300ns } { 0.000ns 4.900ns 1.600ns 1.400ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk1 1 CLK PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ztj:u1\|\\cnt:en 2 REG LC1_E36 14 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1\|\\cnt:en'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { agt1 ztj:u1|numo[5]~167 ztj:u1|numo[3]~174 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { agt1 agt1~out ztj:u1|numo[5]~167 ztj:u1|numo[3]~174 ztj:u1|\cnt:en } { 0.000ns 0.000ns 3.300ns 1.300ns 1.300ns } { 0.000ns 4.900ns 1.600ns 1.400ns 1.000ns } "" } } { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|\cnt:en } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|\cnt:en } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 numo2\[3\] ztj:u1\|numo\[1\] 20.600 ns register " "Info: tco from clock \"clk1\" to destination pin \"numo2\[3\]\" through register \"ztj:u1\|numo\[1\]\" is 20.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk1 1 CLK PIN_126 23 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns ztj:u1\|numo\[1\] 2 REG LC8_E32 9 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_E32; Fanout = 9; REG Node = 'ztj:u1\|numo\[1\]'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { clk1 ztj:u1|numo[1] } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|numo[1] } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|numo[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.700 ns + Longest register pin " "Info: + Longest register to pin delay is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ztj:u1\|numo\[1\] 1 REG LC8_E32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_E32; Fanout = 9; REG Node = 'ztj:u1\|numo\[1\]'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { ztj:u1|numo[1] } "NODE_NAME" } } { "ztj.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/ztj.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.600 ns) 3.600 ns fenwei:u2\|LessThan8~106 2 COMB LC5_F34 2 " "Info: 2: + IC(2.000 ns) + CELL(1.600 ns) = 3.600 ns; Loc. = LC5_F34; Fanout = 2; COMB Node = 'fenwei:u2\|LessThan8~106'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { ztj:u1|numo[1] fenwei:u2|LessThan8~106 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/fenwei.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 5.500 ns fenwei:u2\|LessThan4~60 3 COMB LC2_F34 2 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.500 ns; Loc. = LC2_F34; Fanout = 2; COMB Node = 'fenwei:u2\|LessThan4~60'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { fenwei:u2|LessThan8~106 fenwei:u2|LessThan4~60 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/fenwei.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 7.500 ns fenwei:u2\|numb\[3\]~1651 4 COMB LC1_F34 1 " "Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 7.500 ns; Loc. = LC1_F34; Fanout = 1; COMB Node = 'fenwei:u2\|numb\[3\]~1651'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { fenwei:u2|LessThan4~60 fenwei:u2|numb[3]~1651 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/fenwei.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.400 ns) 10.200 ns fenwei:u2\|numb\[3\]~1653 5 COMB LC7_F36 1 " "Info: 5: + IC(1.300 ns) + CELL(1.400 ns) = 10.200 ns; Loc. = LC7_F36; Fanout = 1; COMB Node = 'fenwei:u2\|numb\[3\]~1653'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { fenwei:u2|numb[3]~1651 fenwei:u2|numb[3]~1653 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/fenwei.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(6.300 ns) 17.700 ns numo2\[3\] 6 PIN PIN_33 0 " "Info: 6: + IC(1.200 ns) + CELL(6.300 ns) = 17.700 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'numo2\[3\]'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { fenwei:u2|numb[3]~1653 numo2[3] } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.600 ns ( 71.19 % ) " "Info: Total cell delay = 12.600 ns ( 71.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 28.81 % ) " "Info: Total interconnect delay = 5.100 ns ( 28.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "17.700 ns" { ztj:u1|numo[1] fenwei:u2|LessThan8~106 fenwei:u2|LessThan4~60 fenwei:u2|numb[3]~1651 fenwei:u2|numb[3]~1653 numo2[3] } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "17.700 ns" { ztj:u1|numo[1] fenwei:u2|LessThan8~106 fenwei:u2|LessThan4~60 fenwei:u2|numb[3]~1651 fenwei:u2|numb[3]~1653 numo2[3] } { 0.000ns 2.000ns 0.300ns 0.300ns 1.300ns 1.200ns } { 0.000ns 1.600ns 1.600ns 1.700ns 1.400ns 6.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { clk1 ztj:u1|numo[1] } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { clk1 clk1~out ztj:u1|numo[1] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "17.700 ns" { ztj:u1|numo[1] fenwei:u2|LessThan8~106 fenwei:u2|LessThan4~60 fenwei:u2|numb[3]~1651 fenwei:u2|numb[3]~1653 numo2[3] } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "17.700 ns" { ztj:u1|numo[1] fenwei:u2|LessThan8~106 fenwei:u2|LessThan4~60 fenwei:u2|numb[3]~1651 fenwei:u2|numb[3]~1653 numo2[3] } { 0.000ns 2.000ns 0.300ns 0.300ns 1.300ns 1.200ns } { 0.000ns 1.600ns 1.600ns 1.700ns 1.400ns 6.300ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rst1 numo2\[2\] 13.300 ns Longest " "Info: Longest tpd from source pin \"rst1\" to destination pin \"numo2\[2\]\" is 13.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns rst1 1 PIN PIN_54 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 17; PIN Node = 'rst1'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst1 } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 3.800 ns fenwei:u2\|numa\[0\]~421 2 COMB LC6_F35 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC6_F35; Fanout = 1; COMB Node = 'fenwei:u2\|numa\[0\]~421'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { rst1 fenwei:u2|numa[0]~421 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/fenwei.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 5.800 ns fenwei:u2\|numb\[2\]~1667 3 COMB LC5_F35 1 " "Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 5.800 ns; Loc. = LC5_F35; Fanout = 1; COMB Node = 'fenwei:u2\|numb\[2\]~1667'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { fenwei:u2|numa[0]~421 fenwei:u2|numb[2]~1667 } "NODE_NAME" } } { "fenwei.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/fenwei.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(6.300 ns) 13.300 ns numo2\[2\] 4 PIN PIN_32 0 " "Info: 4: + IC(1.200 ns) + CELL(6.300 ns) = 13.300 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'numo2\[2\]'" {  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { fenwei:u2|numb[2]~1667 numo2[2] } "NODE_NAME" } } { "jtdkz.vhd" "" { Text "C:/Documents and Settings/lsfy/桌面/jtdkz/jtdkz.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.600 ns ( 87.22 % ) " "Info: Total cell delay = 11.600 ns ( 87.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 12.78 % ) " "Info: Total interconnect delay = 1.700 ns ( 12.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "13.300 ns" { rst1 fenwei:u2|numa[0]~421 fenwei:u2|numb[2]~1667 numo2[2] } "NODE_NAME" } } { "g:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/quartus/quartus/bin/Technology_Viewer.qrui" "13.300 ns" { rst1 rst1~out fenwei:u2|numa[0]~421 fenwei:u2|numb[2]~1667 numo2[2] } { 0.000ns 0.000ns 0.200ns 0.300ns 1.200ns } { 0.000ns 2.000ns 1.600ns 1.700ns 6.300ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}