jtdkz.tan.rpt

这是交通灯控制器的设计系统,里面有文字说明以及详细的图形,希望大家喜欢

+-------+-------------------+-----------------+------+----------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+------------+------+----------------+----------+
; Minimum Slack ; Required th ; Actual th  ; From ; To             ; To Clock ;
+---------------+-------------+------------+------+----------------+----------+
; N/A           ; None        ; 0.500 ns   ; rst1 ; ztj:u1|state.d ; clk1     ;
; N/A           ; None        ; 0.400 ns   ; rst1 ; ztj:u1|state.c ; clk1     ;
; N/A           ; None        ; -1.300 ns  ; rst1 ; ztj:u1|mr      ; clk1     ;
; N/A           ; None        ; -1.300 ns  ; rst1 ; ztj:u1|state.b ; clk1     ;
; N/A           ; None        ; -1.300 ns  ; rst1 ; ztj:u1|my      ; clk1     ;
; N/A           ; None        ; -1.300 ns  ; rst1 ; ztj:u1|br      ; clk1     ;
; N/A           ; None        ; -1.500 ns  ; rst1 ; ztj:u1|state.a ; clk1     ;
; N/A           ; None        ; -2.300 ns  ; rst1 ; ztj:u1|mg      ; clk1     ;
; N/A           ; None        ; -2.300 ns  ; rst1 ; ztj:u1|by      ; clk1     ;
; N/A           ; None        ; -2.300 ns  ; rst1 ; ztj:u1|bg      ; clk1     ;
; N/A           ; None        ; -4.100 ns  ; rst1 ; ztj:u1|numo[1] ; clk1     ;
; N/A           ; None        ; -4.100 ns  ; rst1 ; ztj:u1|numo[4] ; clk1     ;
; N/A           ; None        ; -4.100 ns  ; rst1 ; ztj:u1|numo[0] ; clk1     ;
; N/A           ; None        ; -5.100 ns  ; rst1 ; ztj:u1|\cnt:en ; clk1     ;
; N/A           ; None        ; -5.100 ns  ; rst1 ; ztj:u1|numo[3] ; clk1     ;
; N/A           ; None        ; -5.100 ns  ; rst1 ; ztj:u1|numo[2] ; clk1     ;
; N/A           ; None        ; -5.100 ns  ; rst1 ; ztj:u1|numo[5] ; clk1     ;
; N/A           ; None        ; -7.600 ns  ; sm1  ; ztj:u1|\cnt:en ; clk1     ;
; N/A           ; None        ; -8.000 ns  ; sb1  ; ztj:u1|\cnt:en ; clk1     ;
; N/A           ; None        ; -9.100 ns  ; sm1  ; ztj:u1|state.d ; clk1     ;
; N/A           ; None        ; -9.300 ns  ; sm1  ; ztj:u1|state.c ; clk1     ;
; N/A           ; None        ; -9.400 ns  ; sb1  ; ztj:u1|state.b ; clk1     ;
; N/A           ; None        ; -9.500 ns  ; sb1  ; ztj:u1|state.d ; clk1     ;
; N/A           ; None        ; -9.500 ns  ; sm1  ; ztj:u1|state.b ; clk1     ;
; N/A           ; None        ; -9.700 ns  ; sb1  ; ztj:u1|state.a ; clk1     ;
; N/A           ; None        ; -9.700 ns  ; sb1  ; ztj:u1|state.c ; clk1     ;
; N/A           ; None        ; -9.800 ns  ; sm1  ; ztj:u1|state.a ; clk1     ;
; N/A           ; None        ; -10.100 ns ; agt1 ; ztj:u1|numo[1] ; clk1     ;
; N/A           ; None        ; -10.100 ns ; agt1 ; ztj:u1|numo[4] ; clk1     ;
; N/A           ; None        ; -10.100 ns ; agt1 ; ztj:u1|numo[0] ; clk1     ;
; N/A           ; None        ; -11.100 ns ; agt1 ; ztj:u1|\cnt:en ; clk1     ;
; N/A           ; None        ; -11.100 ns ; agt1 ; ztj:u1|numo[3] ; clk1     ;
; N/A           ; None        ; -11.100 ns ; agt1 ; ztj:u1|numo[2] ; clk1     ;
; N/A           ; None        ; -11.100 ns ; agt1 ; ztj:u1|numo[5] ; clk1     ;
+---------------+-------------+------------+------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Jul 15 17:51:22 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jtdkz -c jtdkz
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk1" has Internal fmax of 64.1 MHz between source register "ztj:u1|\cnt:en" and destination register "ztj:u1|\cnt:en" (period= 15.6 ns)
    Info: + Longest register to register delay is 14.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1|\cnt:en'
        Info: 2: + IC(1.000 ns) + CELL(0.700 ns) = 1.700 ns; Loc. = LC3_E34; Fanout = 2; COMB Node = 'ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]'
        Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 3.100 ns; Loc. = LC4_E34; Fanout = 2; COMB Node = 'ztj:u1|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]'
        Info: 4: + IC(0.900 ns) + CELL(1.600 ns) = 5.600 ns; Loc. = LC4_E35; Fanout = 2; COMB Node = 'ztj:u1|Equal2~38'
        Info: 5: + IC(0.300 ns) + CELL(1.400 ns) = 7.300 ns; Loc. = LC5_E35; Fanout = 2; COMB Node = 'ztj:u1|Equal2~39'
        Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 9.000 ns; Loc. = LC1_E35; Fanout = 4; COMB Node = 'ztj:u1|Equal2~40'
        Info: 7: + IC(0.900 ns) + CELL(1.600 ns) = 11.500 ns; Loc. = LC6_E36; Fanout = 1; COMB Node = 'ztj:u1|Selector4~222'
        Info: 8: + IC(0.300 ns) + CELL(1.400 ns) = 13.200 ns; Loc. = LC8_E36; Fanout = 1; COMB Node = 'ztj:u1|Selector4~223'
        Info: 9: + IC(0.300 ns) + CELL(1.000 ns) = 14.500 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1|\cnt:en'
        Info: Total cell delay = 10.500 ns ( 72.41 % )
        Info: Total interconnect delay = 4.000 ns ( 27.59 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk1" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1|\cnt:en'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "clk1" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1|\cnt:en'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "ztj:u1|\cnt:en" (data pin = "agt1", clock pin = "clk1") is 13.000 ns
    Info: + Longest pin to register delay is 14.800 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_10; Fanout = 2; PIN Node = 'agt1'
        Info: 2: + IC(3.300 ns) + CELL(1.600 ns) = 9.800 ns; Loc. = LC5_E31; Fanout = 7; COMB Node = 'ztj:u1|numo[5]~167'
        Info: 3: + IC(1.300 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC3_E32; Fanout = 7; COMB Node = 'ztj:u1|numo[3]~174'
        Info: 4: + IC(1.300 ns) + CELL(1.000 ns) = 14.800 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1|\cnt:en'
        Info: Total cell delay = 8.900 ns ( 60.14 % )
        Info: Total interconnect delay = 5.900 ns ( 39.86 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk1" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E36; Fanout = 14; REG Node = 'ztj:u1|\cnt:en'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "clk1" to destination pin "numo2[3]" through register "ztj:u1|numo[1]" is 20.600 ns
    Info: + Longest clock path from clock "clk1" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_E32; Fanout = 9; REG Node = 'ztj:u1|numo[1]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 17.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_E32; Fanout = 9; REG Node = 'ztj:u1|numo[1]'
        Info: 2: + IC(2.000 ns) + CELL(1.600 ns) = 3.600 ns; Loc. = LC5_F34; Fanout = 2; COMB Node = 'fenwei:u2|LessThan8~106'
        Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.500 ns; Loc. = LC2_F34; Fanout = 2; COMB Node = 'fenwei:u2|LessThan4~60'
        Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 7.500 ns; Loc. = LC1_F34; Fanout = 1; COMB Node = 'fenwei:u2|numb[3]~1651'
        Info: 5: + IC(1.300 ns) + CELL(1.400 ns) = 10.200 ns; Loc. = LC7_F36; Fanout = 1; COMB Node = 'fenwei:u2|numb[3]~1653'
        Info: 6: + IC(1.200 ns) + CELL(6.300 ns) = 17.700 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'numo2[3]'
        Info: Total cell delay = 12.600 ns ( 71.19 % )
        Info: Total interconnect delay = 5.100 ns ( 28.81 % )
Info: Longest tpd from source pin "rst1" to destination pin "numo2[2]" is 13.300 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 17; PIN Node = 'rst1'
    Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC6_F35; Fanout = 1; COMB Node = 'fenwei:u2|numa[0]~421'
    Info: 3: + IC(0.300 ns) + CELL(1.700 ns) = 5.800 ns; Loc. = LC5_F35; Fanout = 1; COMB Node = 'fenwei:u2|numb[2]~1667'
    Info: 4: + IC(1.200 ns) + CELL(6.300 ns) = 13.300 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'numo2[2]'
    Info: Total cell delay = 11.600 ns ( 87.22 % )
    Info: Total interconnect delay = 1.700 ns ( 12.78 % )
Info: th for register "ztj:u1|state.d" (data pin = "rst1", clock pin = "clk1") is 0.500 ns
    Info: + Longest clock path from clock "clk1" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 23; CLK Node = 'clk1'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_E36; Fanout = 4; REG Node = 'ztj:u1|state.d'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 17; PIN Node = 'rst1'
        Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC2_E36; Fanout = 4; REG Node = 'ztj:u1|state.d'
        Info: Total cell delay = 3.000 ns ( 93.75 % )
        Info: Total interconnect delay = 0.200 ns ( 6.25 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Sun Jul 15 17:51:23 2007
    Info: Elapsed time: 00:00:01