ztj.vhd

这是交通灯控制器的设计系统,里面有文字说明以及详细的图形,希望大家喜欢

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ztj is
port (agt,clk,sm,sb,rst: in bit;
      mr,my,mg,br,by,bg:out bit;
      numo:out integer range 0 to 99);
end ;
architecture one of ztj is
   type state_type is (a,b,c,d);
   signal state: state_type;
   begin
   cnt:process (clk)
   variable s:integer range 0 to 45;
   variable clr,en:bit;
   begin
  if rst='1' then s:=0;
   elsif agt='1' then s:=0;
      mr<='1';my<='0';mg<='0';
      br<='1';by<='0';bg<='0';
      state<=a;
   elsif(clk'event and clk='1') then 
          numo<=s;
          if clr='0' then s:=0;
          elsif en='0' then s:=s;
          else s:=s+1;
          end if;
   case state is 
        when a=>mr<='0';my<='0';mg<='1';
                br<='1';by<='0';bg<='0';
             if (sb and sm)='1' then 
                if s=45 then 
                   state<=b;clr:='0';en:='0';
                else 
                   state<=a;clr:='1';en:='1';
                end if;
             elsif (sb and (not sm))='1' then
                   state<=b;clr:='0';en:='0'; 
             else 
                   state<=a;clr:='1';en:='1';
             end if;
         when b=>mr<='0';my<='1';mg<='0';
                 br<='1';by<='0';bg<='0'; 
             if s=5 then 
                    state<=c;clr:='0';en:='0';
             else  
                    state<=b;clr:='1';en:='1';
             end if;
         when c=>mr<='1';my<='0';mg<='0';
                   br<='0';by<='0';bg<='1';
             if (sm and sb) ='1'  then
                if  s=25 then  
                     state<=d;clr:='0';en:='0';
                else
                     state<=c;clr:='1';en:='1';
                end if;
             elsif sb='0' then 
                     state<=d;clr:='0';en:='0';
             else 
                     state<=c;clr:='1';en:='1';
             end if;
         when d=>mr<='1';my<='0';mg<='0';
                 br<='0';by<='1';bg<='0';
             if  s=5 then 
                     state<=a;clr:='0';en:='0';
             else 
                     state<=d;clr:='1';en:='1';
             end if; 
    end case;
    end if;  
    end process cnt;
end one;