📄 fenwei.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenwei is
port
(numin:in integer range 0 to 99;--输入数值
numa,numb:out integer range 0 to 9;--数值高位,低位
rst:in std_logic);
end;
architecture fen of fenwei is
begin
process(numin)
begin
if rst='1' then numa<=0;
numb<=0;
elsif numin>=90 then
numa<=9;--高位获得值
numb<=numin-90;--低位获得值
elsif numin>=80 then
numa<=8;
numb<=numin-80;
elsif numin>=70 then
numa<=7;
numb<=numin-70;
elsif numin>=60 then
numa<=6;
numb<=numin-60;
elsif numin>=50 then
numa<=5;
numb<=numin-50;
elsif numin>=40 then
numa<=4;
numb<=numin-40;
elsif numin>=30 then
numa<=3;
numb<=numin-30;
elsif numin>=20 then
numa<=2;
numb<=numin-20;
elsif numin>=10 then
numa<=1;
numb<=numin-10;
else
numa<=0;
numb<=numin;
end if;
end process;
end;
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