📄 cnt24.rpt
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Device-Specific Information: d:\vhdl编程\cnt24_t\cnt24.rpt
cnt24
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl编程\cnt24_t\cnt24.rpt
cnt24
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: d:\vhdl编程\cnt24_t\cnt24.rpt
cnt24
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
-- Node name is ':15' = 'QH4'
-- Equation name is 'QH4', location is LC8_A24, type is buried.
QH4 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !CLR & _LC3_A23 & !QH4
# !CLR & !_LC2_A21 & QH4;
-- Node name is ':14' = 'QH5'
-- Equation name is 'QH5', location is LC1_A23, type is buried.
QH5 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !CLR & !_LC2_A23 & QH5
# !CLR & _LC5_A24;
-- Node name is ':13' = 'QH6'
-- Equation name is 'QH6', location is LC3_A24, type is buried.
QH6 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !CLR & _LC1_A24
# !CLR & !_LC2_A21 & QH6;
-- Node name is ':12' = 'QH7'
-- Equation name is 'QH7', location is LC2_A24, type is buried.
QH7 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = !CLR & _LC7_A24
# !CLR & !_LC2_A21 & QH7;
-- Node name is ':19' = 'QL0'
-- Equation name is 'QL0', location is LC3_A21, type is buried.
QL0 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = !CLR & !QL0;
-- Node name is ':18' = 'QL1'
-- Equation name is 'QL1', location is LC1_A21, type is buried.
QL1 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = _LC6_A23 & !QL0 & QL1
# _LC6_A23 & QL0 & !QL1;
-- Node name is ':17' = 'QL2'
-- Equation name is 'QL2', location is LC5_A21, type is buried.
QL2 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !_LC6_A21 & _LC6_A23 & QL2
# _LC6_A21 & _LC6_A23 & !QL2;
-- Node name is ':16' = 'QL3'
-- Equation name is 'QL3', location is LC7_A21, type is buried.
QL3 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = _LC6_A23 & !QL2 & QL3
# !_LC6_A21 & _LC6_A23 & QL3
# _LC6_A21 & _LC6_A23 & QL2 & !QL3;
-- Node name is 'QOUT0'
-- Equation name is 'QOUT0', type is output
QOUT0 = QL0;
-- Node name is 'QOUT1'
-- Equation name is 'QOUT1', type is output
QOUT1 = QL1;
-- Node name is 'QOUT2'
-- Equation name is 'QOUT2', type is output
QOUT2 = QL2;
-- Node name is 'QOUT3'
-- Equation name is 'QOUT3', type is output
QOUT3 = QL3;
-- Node name is 'QOUT4'
-- Equation name is 'QOUT4', type is output
QOUT4 = QH4;
-- Node name is 'QOUT5'
-- Equation name is 'QOUT5', type is output
QOUT5 = QH5;
-- Node name is 'QOUT6'
-- Equation name is 'QOUT6', type is output
QOUT6 = QH6;
-- Node name is 'QOUT7'
-- Equation name is 'QOUT7', type is output
QOUT7 = QH7;
-- Node name is '|LPM_ADD_SUB:147|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ009);
_EQ009 = QH4 & QH5;
-- Node name is '|LPM_ADD_SUB:206|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A21', type is buried
!_LC6_A21 = _LC6_A21~NOT;
_LC6_A21~NOT = LCELL( _EQ010);
_EQ010 = !QL1
# !QL0;
-- Node name is ':84'
-- Equation name is '_LC2_A21', type is buried
!_LC2_A21 = _LC2_A21~NOT;
_LC2_A21~NOT = LCELL( _EQ011);
_EQ011 = !QL3
# QL2
# QL1
# !QL0;
-- Node name is '~107~1'
-- Equation name is '~107~1', location is LC4_A21, type is buried.
-- synthesized logic cell
!_LC4_A21 = _LC4_A21~NOT;
_LC4_A21~NOT = LCELL( _EQ012);
_EQ012 = !_LC6_A21
# QL3
# QL2;
-- Node name is ':108'
-- Equation name is '_LC2_A23', type is buried
!_LC2_A23 = _LC2_A23~NOT;
_LC2_A23~NOT = LCELL( _EQ013);
_EQ013 = !_LC2_A21 & !_LC6_A24
# !_LC2_A21 & !_LC4_A21;
-- Node name is ':122'
-- Equation name is '_LC6_A24', type is buried
!_LC6_A24 = _LC6_A24~NOT;
_LC6_A24~NOT = LCELL( _EQ014);
_EQ014 = QH7
# QH6
# !QH5
# QH4;
-- Node name is '~249~1'
-- Equation name is '~249~1', location is LC3_A23, type is buried.
-- synthesized logic cell
_LC3_A23 = LCELL( _EQ015);
_EQ015 = _LC2_A23 & !_LC6_A24;
-- Node name is ':249'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ016);
_EQ016 = _LC3_A23 & !_LC4_A24 & QH7
# _LC3_A23 & !QH6 & QH7
# _LC3_A23 & _LC4_A24 & QH6 & !QH7;
-- Node name is ':255'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ017);
_EQ017 = _LC3_A23 & !QH5 & QH6
# _LC3_A23 & !QH4 & QH6
# _LC3_A23 & QH4 & QH5 & !QH6;
-- Node name is ':261'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ018);
_EQ018 = _LC3_A23 & !QH4 & QH5
# _LC3_A23 & QH4 & !QH5;
-- Node name is '~312~1'
-- Equation name is '~312~1', location is LC6_A23, type is buried.
-- synthesized logic cell
_LC6_A23 = LCELL( _EQ019);
_EQ019 = !CLR & !_LC2_A23;
Project Information d:\vhdl编程\cnt24_t\cnt24.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,303K
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