sdr_sdram.prj

基于VHDL编写的SDR-SDRAM控制器的编程

#-- Synplicity, Inc.
#-- Synplify version 5.3.1
#-- Project file D:\Projects\altera\lpcores\sdr\release\VHDL\V1_0\synthesis\synplicity\sdr_sdram.prj
#-- Written on Tue Jun 06 11:39:39 2000

#device options
set_option -technology APEX20K
set_option -part EP20K400E
set_option -package FC672
set_option -speed_grade -1X

#add_file options
add_file -vhdl -lib work "command.vhd"
add_file -vhdl -lib work "sdr_data_path.vhd"
add_file -vhdl -lib work "control_interface.vhd"
add_file -vhdl -lib work "sdr_sdram.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
set_option -resource_sharing true

#map options
set_option -frequency 133.000
set_option -disable_io_insertion false
set_option -map_logic true
set_option -cliquing false

#simulation options
set_option -write_verilog false
set_option -write_vhdl false

#automatic place and route (vendor) options
set_option -write_apr_constraint true

#MTI Cross Probe options
set_option -mti_root ""

#set result format/file last
project -result_format "edif"
project -result_file "sdr_sdram.vqm"