readme.txt

来自「基于VHDL编写的SDR-SDRAM控制器的编程」· 文本 代码 · 共 18 行

SDR SDRAM Controller VHDL Reference Design version 1.1.


This readme files describes the contents of each directory of the SDR SDRAM Controller reference design version 1.1.


File/Directory				Description
=============================================================================
\doc				SDR SDRAM reference design documentation
\model				Contains the vhdl SDRAM model
\route				Contains the Quartus 2000.05 project files a routed controller design
\simulation			Contains the vhdl testbench, modelsim project file, and library
\source				Contains the vhdl source files for the SDR SDRAM reference design
\synthesis\synplicity		Contains all synplicity project files associated with synthesizing the reference design