sdr_sdram.vqm

基于VHDL编写的SDR-SDRAM控制器的编程

	.dataa(command_delay[3]),
	.datab(G_186),
	.aclr(RESET_N_i)
);
defparam command_delay_2_.operation_mode="normal";
defparam command_delay_2_.output_mode="reg_only";
defparam command_delay_2_.packed_mode="false";
defparam command_delay_2_.lut_mask="bbbb";
// @2:127
  apex20k_lcell command_delay_3_ (
	.regout(command_delay[3]),
	.clk(clk133),
	.dataa(command_delay[4]),
	.datab(G_186),
	.aclr(RESET_N_i)
);
defparam command_delay_3_.operation_mode="normal";
defparam command_delay_3_.output_mode="reg_only";
defparam command_delay_3_.packed_mode="false";
defparam command_delay_3_.lut_mask="bbbb";
// @2:127
  apex20k_lcell command_delay_4_ (
	.regout(command_delay[4]),
	.clk(clk133),
	.dataa(command_delay[5]),
	.datab(G_186),
	.aclr(RESET_N_i)
);
defparam command_delay_4_.operation_mode="normal";
defparam command_delay_4_.output_mode="reg_only";
defparam command_delay_4_.packed_mode="false";
defparam command_delay_4_.lut_mask="bbbb";
// @2:127
  apex20k_lcell command_delay_5_ (
	.regout(command_delay[5]),
	.clk(clk133),
	.dataa(command_delay[6]),
	.datab(G_186),
	.aclr(RESET_N_i)
);
defparam command_delay_5_.operation_mode="normal";
defparam command_delay_5_.output_mode="reg_only";
defparam command_delay_5_.packed_mode="false";
defparam command_delay_5_.lut_mask="bbbb";
// @2:127
  apex20k_lcell command_delay_6_ (
	.regout(command_delay[6]),
	.clk(clk133),
	.dataa(command_delay[7]),
	.datab(G_186),
	.aclr(RESET_N_i)
);
defparam command_delay_6_.operation_mode="normal";
defparam command_delay_6_.output_mode="reg_only";
defparam command_delay_6_.packed_mode="false";
defparam command_delay_6_.lut_mask="bbbb";
// @2:127
  apex20k_lcell command_delay_7_ (
	.regout(command_delay[7]),
	.clk(clk133),
	.dataa(N_307_i),
	.aclr(RESET_N_i)
);
defparam command_delay_7_.operation_mode="normal";
defparam command_delay_7_.output_mode="reg_only";
defparam command_delay_7_.packed_mode="false";
defparam command_delay_7_.lut_mask="aaaa";
// @2:326
  apex20k_lcell CS_N_i_0_ (
	.regout(CS_N_i[0]),
	.clk(clk133),
	.dataa(SADDR[22]),
	.datab(do_refresh),
	.datac(do_precharge),
	.datad(do_load_mode),
	.aclr(RESET_N_i)
);
defparam CS_N_i_0_.operation_mode="normal";
defparam CS_N_i_0_.output_mode="reg_only";
defparam CS_N_i_0_.packed_mode="false";
defparam CS_N_i_0_.lut_mask="fffd";
// @2:326
  apex20k_lcell CS_N_1_ (
	.regout(CS_N[1]),
	.clk(clk133),
	.dataa(SADDR[22]),
	.datab(do_refresh),
	.datac(do_precharge),
	.datad(do_load_mode),
	.aclr(RESET_N_i)
);
defparam CS_N_1_.operation_mode="normal";
defparam CS_N_1_.output_mode="reg_only";
defparam CS_N_1_.packed_mode="false";
defparam CS_N_1_.lut_mask="0001";
// @2:127
  apex20k_lcell rp_shift_0_ (
	.regout(rp_shift[0]),
	.clk(clk133),
	.dataa(rp_shift[1]),
	.datab(command_done),
	.datac(command_delay[0]),
	.aclr(RESET_N_i)
);
defparam rp_shift_0_.operation_mode="normal";
defparam rp_shift_0_.output_mode="reg_only";
defparam rp_shift_0_.packed_mode="false";
defparam rp_shift_0_.lut_mask="aeae";
// @2:127
  apex20k_lcell rp_shift_1_ (
	.regout(rp_shift[1]),
	.clk(clk133),
	.dataa(rp_shift[2]),
	.datab(command_done),
	.datac(command_delay[0]),
	.aclr(RESET_N_i)
);
defparam rp_shift_1_.operation_mode="normal";
defparam rp_shift_1_.output_mode="reg_only";
defparam rp_shift_1_.packed_mode="false";
defparam rp_shift_1_.lut_mask="aeae";
// @2:127
  apex20k_lcell rp_shift_2_ (
	.regout(rp_shift[2]),
	.clk(clk133),
	.dataa(rp_shift[3]),
	.datab(command_done),
	.datac(command_delay[0]),
	.aclr(RESET_N_i)
);
defparam rp_shift_2_.operation_mode="normal";
defparam rp_shift_2_.output_mode="reg_only";
defparam rp_shift_2_.packed_mode="false";
defparam rp_shift_2_.lut_mask="aeae";
// @2:127
  apex20k_lcell rp_shift_3_ (
	.regout(rp_shift[3]),
	.clk(clk133),
	.dataa(command_delay[0]),
	.datab(command_done),
	.aclr(RESET_N_i)
);
defparam rp_shift_3_.operation_mode="normal";
defparam rp_shift_3_.output_mode="reg_only";
defparam rp_shift_3_.packed_mode="false";
defparam rp_shift_3_.lut_mask="4444";
// @2:326
  apex20k_lcell BA_0_ (
	.regout(BA[0]),
	.clk(clk133),
	.dataa(SADDR[20]),
	.datab(do_precharge),
	.datac(do_load_mode),
	.aclr(RESET_N_i)
);
defparam BA_0_.operation_mode="normal";
defparam BA_0_.output_mode="reg_only";
defparam BA_0_.packed_mode="false";
defparam BA_0_.lut_mask="0202";
// @2:326
  apex20k_lcell BA_1_ (
	.regout(BA[1]),
	.clk(clk133),
	.dataa(SADDR[21]),
	.datab(do_precharge),
	.datac(do_load_mode),
	.aclr(RESET_N_i)
);
defparam BA_1_.operation_mode="normal";
defparam BA_1_.output_mode="reg_only";
defparam BA_1_.packed_mode="false";
defparam BA_1_.lut_mask="0202";
assign SC_BL[1] = SC_BL_1;
assign SC_BL[2] = SC_BL_2;
assign SC_BL[0] = SC_BL_0;
assign SC_BL[3] = SC_BL_3;
assign SA_0 = SA[0];
assign SA_1 = SA[1];
assign SA_2 = SA[2];
assign SA_3 = SA[3];
assign SA_4 = SA[4];
assign SA_5 = SA[5];
assign SA_6 = SA[6];
assign SA_7 = SA[7];
assign SA_8 = SA[8];
assign SA_9 = SA[9];
assign SA_10 = SA[10];
assign SA_11 = SA[11];
assign SC_RC[1] = SC_RC_1;
assign SC_RC[0] = SC_RC_0;
assign CS_N_i_0 = CS_N_i[0];
assign CS_N_0 = CS_N[1];
assign SADDR[19] = SADDR_19;
assign SADDR[0] = SADDR_0;
assign SADDR[9] = SADDR_9;
assign SADDR[1] = SADDR_1;
assign SADDR[10] = SADDR_10;
assign SADDR[2] = SADDR_2;
assign SADDR[11] = SADDR_11;
assign SADDR[3] = SADDR_3;
assign SADDR[12] = SADDR_12;
assign SADDR[4] = SADDR_4;
assign SADDR[13] = SADDR_13;
assign SADDR[5] = SADDR_5;
assign SADDR[14] = SADDR_14;
assign SADDR[6] = SADDR_6;
assign SADDR[15] = SADDR_15;
assign SADDR[7] = SADDR_7;
assign SADDR[16] = SADDR_16;
assign SADDR[8] = SADDR_8;
assign SADDR[17] = SADDR_17;
assign SADDR[18] = SADDR_18;
assign SADDR[22] = SADDR_22;
assign SADDR[20] = SADDR_20;
assign SADDR[21] = SADDR_21;
assign BA_0 = BA[0];
assign BA_1 = BA[1];
endmodule /* command */

module control_interface (
  CMD_c_0,
  CMD_c_2,
  CMD_c_1,
  SC_BL_0,
  SC_BL_1,
  SC_BL_2,
  SC_BL_3,
  SC_RC_0,
  SC_RC_1,
  ADDR_c_0,
  ADDR_c_1,
  ADDR_c_2,
  ADDR_c_3,
  ADDR_c_4,
  ADDR_c_5,
  ADDR_c_6,
  ADDR_c_7,
  ADDR_c_8,
  ADDR_c_9,
  ADDR_c_10,
  ADDR_c_11,
  ADDR_c_12,
  ADDR_c_13,
  ADDR_c_14,
  ADDR_c_15,
  ADDR_c_16,
  ADDR_c_17,
  ADDR_c_18,
  ADDR_c_19,
  ADDR_c_20,
  ADDR_c_21,
  ADDR_c_22,
  SADDR_0,
  SADDR_1,
  SADDR_2,
  SADDR_3,
  SADDR_4,
  SADDR_5,
  SADDR_6,
  SADDR_7,
  SADDR_8,
  SADDR_9,
  SADDR_10,
  SADDR_11,
  SADDR_12,
  SADDR_13,
  SADDR_14,
  SADDR_15,
  SADDR_16,
  SADDR_17,
  SADDR_18,
  SADDR_19,
  SADDR_20,
  SADDR_21,
  SADDR_22,
  sc_pm_i,
  REF_ACK,
  un11_sc_bl_int_1,
  SC_PM,
  LOAD_MODE,
  PRECHARGE,
  READA,
  REFRESH,
  WRITEA,
  CM_ACK,
  CMD_ACK,
  REF_REQ,
  RESET_N_i,
  clk133
);
input CMD_c_0;
input CMD_c_2;
input CMD_c_1;
output SC_BL_0;
output SC_BL_1;
output SC_BL_2;
output SC_BL_3;
output SC_RC_0;
output SC_RC_1;
input ADDR_c_0;
input ADDR_c_1;
input ADDR_c_2;
input ADDR_c_3;
input ADDR_c_4;
input ADDR_c_5;
input ADDR_c_6;
input ADDR_c_7;
input ADDR_c_8;
input ADDR_c_9;
input ADDR_c_10;
input ADDR_c_11;
input ADDR_c_12;
input ADDR_c_13;
input ADDR_c_14;
input ADDR_c_15;
input ADDR_c_16;
input ADDR_c_17;
input ADDR_c_18;
input ADDR_c_19;
input ADDR_c_20;
input ADDR_c_21;
input ADDR_c_22;
output SADDR_0;
output SADDR_1;
output SADDR_2;
output SADDR_3;
output SADDR_4;
output SADDR_5;
output SADDR_6;
output SADDR_7;
output SADDR_8;
output SADDR_9;
output SADDR_10;
output SADDR_11;
output SADDR_12;
output SADDR_13;
output SADDR_14;
output SADDR_15;
output SADDR_16;
output SADDR_17;
output SADDR_18;
output SADDR_19;
output SADDR_20;
output SADDR_21;
output SADDR_22;
output sc_pm_i;
input REF_ACK;
output un11_sc_bl_int_1;
output SC_PM;
output LOAD_MODE;
output PRECHARGE;
output READA;
output REFRESH;
output WRITEA;
input CM_ACK;
output CMD_ACK;
output REF_REQ;
input RESET_N_i;
input clk133;
wire CMD_c_0 ;
wire CMD_c_2 ;
wire CMD_c_1 ;
wire SC_BL_0 ;
wire SC_BL_1 ;
wire SC_BL_2 ;
wire SC_BL_3 ;
wire SC_RC_0 ;
wire SC_RC_1 ;
wire ADDR_c_0 ;
wire ADDR_c_1 ;
wire ADDR_c_2 ;
wire ADDR_c_3 ;
wire ADDR_c_4 ;
wire ADDR_c_5 ;
wire ADDR_c_6 ;
wire ADDR_c_7 ;
wire ADDR_c_8 ;
wire ADDR_c_9 ;
wire ADDR_c_10 ;
wire ADDR_c_11 ;
wire ADDR_c_12 ;
wire ADDR_c_13 ;
wire ADDR_c_14 ;
wire ADDR_c_15 ;
wire ADDR_c_16 ;
wire ADDR_c_17 ;
wire ADDR_c_18 ;
wire ADDR_c_19 ;
wire ADDR_c_20 ;
wire ADDR_c_21 ;
wire ADDR_c_22 ;
wire SADDR_0 ;
wire SADDR_1 ;
wire SADDR_2 ;
wire SADDR_3 ;
wire SADDR_4 ;
wire SADDR_5 ;
wire SADDR_6 ;
wire SADDR_7 ;
wire SADDR_8 ;
wire SADDR_9 ;
wire SADDR_10 ;
wire SADDR_11 ;
wire SADDR_12 ;
wire SADDR_13 ;
wire SADDR_14 ;
wire SADDR_15 ;
wire SADDR_16 ;
wire SADDR_17 ;
wire SADDR_18 ;
wire SADDR_19 ;
wire SADDR_20 ;
wire SADDR_21 ;
wire SADDR_22 ;
wire sc_pm_i ;
wire REF_ACK ;
wire un11_sc_bl_int_1 ;
wire SC_PM ;
wire LOAD_MODE ;
wire PRECHARGE ;
wire READA ;
wire REFRESH ;
wire WRITEA ;
wire CM_ACK ;
wire CMD_ACK ;
wire REF_REQ ;
wire RESET_N_i ;
wire clk133 ;
wire [14:0] timer_cout;
wire [22:0] SADDR;
wire [22:0] ADDR_c;
wire [1:0] SC_RC;
wire [15:0] ref_per;
wire [2:0] CMD_c;
wire [15:0] timer;
wire [3:0] SC_BL;
wire load_reg2 ;
wire load_reg1 ;
wire G_77 ;
wire G_78 ;
wire G_77_cascout ;
wire G_75 ;
wire G_75_cascout ;
wire G_79 ;
wire G_78_cascout ;
wire un1_un1_ref_ack_i_0_0_and2 ;
wire N_131_i ;
wire G_1_i_and2_0_and2 ;
wire N_61_i ;
wire un1_un1_ref_ack_i_0_0 ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign  sc_pm_i = ~ SC_PM;
  assign  N_61_i = ~ un1_un1_ref_ack_i_0_0;
  assign  N_131_i = ~ G_1_i_and2_0_and2;
// @6:231
  apex20k_lcell un11_sc_bl_int_1_0 (
	.combout(un11_sc_bl_int_1),
	.dataa(SC_BL[1]),
	.datab(SC_BL[0])
);
defparam un11_sc_bl_int_1_0.operation_mode="normal";
defparam un11_sc_bl_int_1_0.output_mode="comb_only";
defparam un11_sc_bl_int_1_0.packed_mode="false";
defparam un11_sc_bl_int_1_0.lut_mask="1111";
// @6:239
  apex20k_lcell un1_un1_ref_ack_i_0_0_Z (
	.combout(un1_un1_ref_ack_i_0_0),
	.dataa(REF_ACK),
	.datab(un1_un1_ref_ack_i_0_0_and2)
);
defparam un1_un1_ref_ack_i_0_0_Z.operation_mode="normal";
defparam un1_un1_ref_ack_i_0_0_Z.output_mode="comb_only";
defparam un1_un1_ref_ack_i_0_0_Z.packed_mode="false";
defparam un1_un1_ref_ack_i_0_0_Z.lut_mask="1111";
// @6:239
  apex20k_lcell un1_un1_ref_ack_i_0_0_and2_Z (
	.combout(un1_un1_ref_ack_i_0_0_and2),
	.dataa(un11_sc_bl_int_1),
	.datab(G_79),
	.datac(SC_BL[3]),
	.datad(SC_BL[2]),
	.cascin(G_78_cascout)
);
defparam un1_un1_ref_ack_i_0_0_and2_Z.operation_mode="normal";
defparam un1_un1_ref_ack_i_0_0_and2_Z.output_mode="comb_only";
defparam un1_un1_ref_ack_i_0_0_and2_Z.packed_mode="false";
defparam un1_un1_ref_ack_i_0_0_and2_Z.lut_mask="ccc4";
// @6:239
  apex20k_lcell un1_un1_ref_ack_i_0_0_and2_G_79 (
	.combout(G_79),
	.dataa(timer[2]),
	.datab(timer[3]),
	.datac(timer[0]),
	.datad(timer[1]),
	.cascin(G_75_cascout)
);
defparam un1_un1_ref_ack_i_0_0_and2_G_79.operation_mode="normal";
defparam un1_un1_ref_ack_i_0_0_and2_G_79.output_mode="comb_only";
defparam un1_un1_ref_ack_i_0_0_and2_G_79.packed_mode="false";
defparam un1_un1_ref_ack_i_0_0_and2_G_79.lut_mask="0001";
// @6:239
  apex20k_lcell un1_un1_ref_ack_i_0_0_and2_G_75 (
	.combout(G_75),
	.cascout(G_75_cascout),
	.dataa(timer[4]),
	.datab(timer[5]),
	.datac(timer[6]),
	.datad(timer[7])
);
defparam un1_un1_ref_ack_i_0_0_and2_G_75.operation_mode="normal";
defparam un1_un1_ref_ack_i_0_0_and2_G_75.output_mode="comb_only";
defparam un1_un1_ref_ack_i_0_0_and2_G_75.packed_mode="false";
defparam un1_un1_ref_ack_i_0_0_and2_G_75.lut_mask="0001";
// @6:239
  apex20k_lcell un1_un1_ref_ack_i_0_0_and2_G_78 (
	.combout(G_78),
	.cascout(G_78_cascout),
	.dataa(timer[10]),
	.datab(timer[11]),
	.datac(timer[8]),
	.datad(timer[9]),
	.cascin(G_77_cascout)
);
defparam un1_un1_ref_ack_i_0_0_and2_G_78.operation_mode="normal";
defparam un1_un1_ref_ack_i_0_0_and2_G_78.output_mode="comb_only";
defparam un1_un1_ref_ack_i_0_0_and2_G_78.packed_mode="false";
defparam un1_un1_ref_ack_i_0_0_and2_G_78.lut_mask="0001";
// @6:239
  apex20k_lcell un1_un1_ref_ack_i_0_0_and2_G_77 (
	.combout(G_77),
	.cascout(G_77_cascout),
	.dataa(timer[12]),
	.datab(timer[13]),
	.datac(timer[14]),
	.datad(timer[15])
);
defparam un1_un1_ref_ack_i_0_0_and2_G_77.operation_mode="normal";
defparam un1_un1_ref_ack_i_0_0_and2_G_77.output_mode="comb_only";
defparam un1_un1_ref_ack_i_0_0_and2_G_77.packed_mode="false";
defparam un1_un1_ref_ack