mt48lc8m16a2.vhd

基于VHDL编写的SDR-SDRAM控制器的编程

                                    SEVERITY WARNING;
                            ELSIF Ba = "01" AND Pc_b1 = '1' THEN
                                Act_b1 := '1';
                                Pc_b1 := '0';
                                B1_row_addr := TO_BITVECTOR (Addr);
                                RCD_chk1 := NOW;
                                RAS_chk1 := NOW;
                                -- Precharge to Active Bank 1
                                ASSERT (NOW - RP_chk1 >= tRP)
                                    REPORT "tRP violation during Activate Bank 1"
                                    SEVERITY WARNING;
                            ELSIF Ba = "10" AND Pc_b2 = '1' THEN
                                Act_b2 := '1';
                                Pc_b2 := '0';
                                B2_row_addr := TO_BITVECTOR (Addr);
                                RCD_chk2 := NOW;
                                RAS_chk2 := NOW;
                                -- Precharge to Active Bank 2
                                ASSERT (NOW - RP_chk2 >= tRP)
                                    REPORT "tRP violation during Activate Bank 2"
                                    SEVERITY WARNING;
                            ELSIF Ba = "11" AND Pc_b3 = '1' THEN
                                Act_b3 := '1';
                                Pc_b3 := '0';
                                B3_row_addr := TO_BITVECTOR (Addr);
                                RCD_chk3 := NOW;
                                RAS_chk3 := NOW;
                                -- Precharge to Active Bank 3
                                ASSERT (NOW - RP_chk3 >= tRP)
                                    REPORT "tRP violation during Activate Bank 3"
                                    SEVERITY WARNING;
                            ELSIF Ba = "00" AND Pc_b0 = '0' THEN
                                ASSERT (FALSE)
                                    REPORT "Bank 0 is not Precharged"
                                    SEVERITY WARNING;
                            ELSIF Ba = "01" AND Pc_b1 = '0' THEN
                                ASSERT (FALSE)
                                    REPORT "Bank 1 is not Precharged"
                                    SEVERITY WARNING;
                            ELSIF Ba = "10" AND Pc_b2 = '0' THEN
                                ASSERT (FALSE)
                                    REPORT "Bank 2 is not Precharged"
                                    SEVERITY WARNING;
                            ELSIF Ba = "11" AND Pc_b3 = '0' THEN
                                ASSERT (FALSE)
                                    REPORT "Bank 3 is not Precharged"
                                    SEVERITY WARNING;
                            END IF;
                            -- Active Bank A to Active Bank B
                            IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
                                ASSERT (FALSE)
                                    REPORT "tRRD violation during Activate"
                                    SEVERITY WARNING;
                            END IF;
                            -- LMR to ACT
                            ASSERT (MRD_chk >= tMRD)
                                REPORT "tMRD violation during Activate"
                                SEVERITY WARNING;
                            -- AutoRefresh to Activate
                            ASSERT (NOW - RC_chk >= tRC)
                                REPORT "tRC violation during Activate"
                                SEVERITY WARNING;
                            -- Record variable for checking violation
                            RRD_chk := NOW;
                            Previous_bank := TO_BITVECTOR (Ba);
                        END IF;
                        
                        -- Precharge Block
                        IF Prech_enable = '1' THEN
                            IF Addr(10) = '1' THEN
                                Pc_b0 := '1'; 
                                Pc_b1 := '1'; 
                                Pc_b2 := '1'; 
                                Pc_b3 := '1';
                                Act_b0 := '0';
                                Act_b1 := '0';
                                Act_b2 := '0';
                                Act_b3 := '0';
                                RP_chk0 := NOW;
                                RP_chk1 := NOW;
                                RP_chk2 := NOW;
                                RP_chk3 := NOW;
                                -- Activate to Precharge all banks
                                ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
                                    REPORT "tRAS violation during Precharge all banks"
                                    SEVERITY WARNING;
                                -- tWR violation check for Write
                                IF ((WR_chk(0) < tWR) OR (WR_chk(1) < tWR) OR
                                    (WR_chk(2) < tWR) OR (WR_chk(3) < tWR)) THEN
                                    ASSERT (FALSE)
                                        REPORT "tWR violation during Precharge ALL banks"
                                        SEVERITY WARNING;
                                END IF;
                            ELSIF Addr(10) = '0' THEN
                                IF Ba = "00" THEN
                                    Pc_b0 := '1';
                                    Act_b0 := '0';
                                    RP_chk0 := NOW;
                                    -- Activate to Precharge bank 0
                                    ASSERT (NOW - RAS_chk0 >= tRAS)
                                        REPORT "tRAS violation during Precharge bank 0"
                                        SEVERITY WARNING;
                                ELSIF Ba = "01" THEN
                                    Pc_b1 := '1';
                                    Act_b1 := '0';
                                    RP_chk1 := NOW;
                                    -- Activate to Precharge bank 1
                                    ASSERT (NOW - RAS_chk1 >= tRAS)
                                        REPORT "tRAS violation during Precharge bank 1"
                                        SEVERITY WARNING;
                                ELSIF Ba = "10" THEN
                                    Pc_b2 := '1';
                                    Act_b2 := '0';
                                    RP_chk2 := NOW;
                                    -- Activate to Precharge bank 2
                                    ASSERT (NOW - RAS_chk2 >= tRAS)
                                        REPORT "tRAS violation during Precharge bank 2"
                                        SEVERITY WARNING;
                                ELSIF Ba = "11" THEN
                                    Pc_b3 := '1';
                                    Act_b3 := '0';
                                    RP_chk3 := NOW;
                                    -- Activate to Precharge bank 3
                                    ASSERT (NOW - RAS_chk3 >= tRAS)
                                        REPORT "tRAS violation during Precharge bank 3"
                                        SEVERITY WARNING;
                                END IF;
                                -- tWR violation check for Write
                                ASSERT (WR_chk(TO_INTEGER(Ba)) >= tWR)
                                    REPORT "tWR violation during Precharge"
                                    SEVERITY WARNING;
                            END IF;
                            -- Terminate a Write Immediately (if same bank or all banks)
                            IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
                                Data_in_enable := '0';
                            END IF;
                            -- Precharge Command Pipeline for READ
                            IF CAS_latency_3 = '1' THEN
                                Command(2) := PRECH;
                                Bank_precharge(2) := TO_BITVECTOR (Ba);
                                A10_precharge(2) := TO_BIT(Addr(10));
                            ELSIF CAS_latency_2 = '1' THEN
                                Command(1) := PRECH;
                                Bank_precharge(1) := TO_BITVECTOR (Ba);
                                A10_precharge(1) := TO_BIT(Addr(10));
                            END IF;
                            -- Record Current tRP time
                            RP_chk := NOW;
                        END IF;
                        
                        -- Burst Terminate
                        IF Burst_term = '1' THEN
                            -- Terminate a Write immediately
                            IF Data_in_enable = '1' THEN
                                Data_in_enable := '0';
                            END IF;
                            -- Terminate a Read depend on CAS Latency
                            IF CAS_latency_3 = '1' THEN
                                Command(2) := BST;
                            ELSIF CAS_latency_2 = '1' THEN
                                Command(1) := BST;
                            END IF;
                        END IF;
                        
                        -- Read, Write, Column Latch
                        IF Read_enable = '1' OR Write_enable = '1' THEN
                            -- Check to see if bank is open (ACT) for Read or Write
                            IF ((Ba = "00" AND Pc_b0 = '1') OR (Ba = "01" AND Pc_b1 = '1') OR (Ba = "10" AND Pc_b2 = '1') OR (Ba = "11" AND Pc_b3 = '1')) THEN
                                ASSERT (FALSE)
                                    REPORT "Cannot Read or Write - Bank is not Activated"
                                    SEVERITY WARNING;
                            END IF;
                            -- Activate to Read or Write
                            IF Ba = "00" THEN
                                ASSERT (NOW - RCD_chk0 >= tRCD)
                                    REPORT "tRCD violation during Read or Write to Bank 0"
                                    SEVERITY WARNING;
                            ELSIF Ba = "01" THEN
                                ASSERT (NOW - RCD_chk1 >= tRCD)
                                    REPORT "tRCD violation during Read or Write to Bank 1"
                                    SEVERITY WARNING;
                            ELSIF Ba = "10" THEN
                                ASSERT (NOW - RCD_chk2 >= tRCD)
                                    REPORT "tRCD violation during Read or Write to Bank 2"
                                    SEVERITY WARNING;
                            ELSIF Ba = "11" THEN
                                ASSERT (NOW - RCD_chk3 >= tRCD)
                                    REPORT "tRCD violation during Read or Write to Bank 3"
                                    SEVERITY WARNING;
                            END IF;

                            -- Read Command
                            IF Read_enable = '1' THEN
                                -- CAS Latency Pipeline
                                IF Cas_latency_3 = '1' THEN
                                    IF Addr(10) = '1' THEN
                                        Command(2) := READ_A;
                                    ELSE
                                        Command(2) := READ;
                                    END IF;
                                    Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
                                    Bank_addr (2) := TO_BITVECTOR (Ba);
                                ELSIF Cas_latency_2 = '1' THEN
                                    IF Addr(10) = '1' THEN
                                        Command(1) := READ_A;
                                    ELSE
                                        Command(1) := READ;
                                    END IF;
                                    Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
                                    Bank_addr (1) := TO_BITVECTOR (Ba);
                                END IF;

                                -- Read intterupt a Write (terminate Write immediately)
                                IF Data_in_enable = '1' THEN
                                    Data_in_enable := '0';
                                    IF Auto_precharge(TO_INTEGER(Bank)) = '1' AND Write_precharge(TO_INTEGER(Bank)) = '1' THEN
                                        RW_interrupt_write(TO_INTEGER(Bank)) := '1';
                                    END IF;
                                END IF;

                                -- Read interrupt a Read (terminate Read after CL)
                                IF Data_out_enable = '1' THEN
                                    IF Auto_precharge(TO_INTEGER(Bank)) = '1' AND Read_precharge(TO_INTEGER(Bank)) = '1' THEN
                                        RW_interrupt_read(TO_INTEGER(Bank)) := '1';
                                    END IF;