📄 stopwatch.map.rpt
字号:
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:i_rtl_3
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- act:u4
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------+
; |stopwatch ; 159 (0) ; 39 ; 0 ; 17 ; 120 (0) ; 4 (0) ; 35 (0) ; 45 (0) ; |stopwatch ;
; |act:u4| ; 63 (63) ; 13 ; 0 ; 0 ; 50 (50) ; 2 (2) ; 11 (11) ; 0 (0) ; |stopwatch|act:u4 ;
; |minute:u3| ; 30 (15) ; 8 ; 0 ; 0 ; 22 (7) ; 0 (0) ; 8 (8) ; 15 (0) ; |stopwatch|minute:u3 ;
; |lpm_add_sub:i_rtl_0| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |stopwatch|minute:u3|lpm_add_sub:i_rtl_0 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |stopwatch|minute:u3|lpm_add_sub:i_rtl_0|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |stopwatch|minute:u3|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_3| ; 8 (0) ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; |stopwatch|minute:u3|lpm_add_sub:i_rtl_3 ;
; |addcore:adder| ; 8 (1) ; 0 ; 0 ; 0 ; 8 (1) ; 0 (0) ; 0 (0) ; 8 (1) ; |stopwatch|minute:u3|lpm_add_sub:i_rtl_3|addcore:adder ;
; |a_csnbuffer:result_node| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; |stopwatch|minute:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node ;
; |msecond:u1| ; 34 (19) ; 9 ; 0 ; 0 ; 25 (10) ; 1 (1) ; 8 (8) ; 15 (0) ; |stopwatch|msecond:u1 ;
; |lpm_add_sub:i_rtl_2| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |stopwatch|msecond:u1|lpm_add_sub:i_rtl_2 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |stopwatch|msecond:u1|lpm_add_sub:i_rtl_2|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |stopwatch|msecond:u1|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_5| ; 8 (0) ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; |stopwatch|msecond:u1|lpm_add_sub:i_rtl_5 ;
; |addcore:adder| ; 8 (1) ; 0 ; 0 ; 0 ; 8 (1) ; 0 (0) ; 0 (0) ; 8 (1) ; |stopwatch|msecond:u1|lpm_add_sub:i_rtl_5|addcore:adder ;
; |a_csnbuffer:result_node| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; |stopwatch|msecond:u1|lpm_add_sub:i_rtl_5|addcore:adder|a_csnbuffer:result_node ;
; |second:u2| ; 32 (17) ; 9 ; 0 ; 0 ; 23 (8) ; 1 (1) ; 8 (8) ; 15 (0) ; |stopwatch|second:u2 ;
; |lpm_add_sub:i_rtl_1| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |stopwatch|second:u2|lpm_add_sub:i_rtl_1 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |stopwatch|second:u2|lpm_add_sub:i_rtl_1|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |stopwatch|second:u2|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_4| ; 8 (0) ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; |stopwatch|second:u2|lpm_add_sub:i_rtl_4 ;
; |addcore:adder| ; 8 (1) ; 0 ; 0 ; 0 ; 8 (1) ; 0 (0) ; 0 (0) ; 8 (1) ; |stopwatch|second:u2|lpm_add_sub:i_rtl_4|addcore:adder ;
; |a_csnbuffer:result_node| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; |stopwatch|second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node ;
+---------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in E:/vdhl试验/stopwatch/stopwatch.map.eqn.
+-----------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+------------------------------------------------------------
; File Name ; Read ;
+----------------------------------------------------+------+
; act.vhd ; Read ;
; minute.vhd ; Read ;
; msecond.vhd ; Read ;
; second.vhd ; Read ;
; stopwatch.vhd ; Read ;
; c:/quartus/libraries/megafunctions/lpm_add_sub.tdf ; Read ;
; c:/quartus/libraries/megafunctions/addcore.tdf ; Read ;
; c:/quartus/libraries/megafunctions/a_csnbuffer.tdf ; Read ;
; c:/quartus/libraries/megafunctions/altshift.tdf ; Read ;
+----------------------------------------------------+------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+-------------------------------+-------------+
; Logic cells ; 159 ;
; Total combinational functions ; 155 ;
; Total registers ; 39 ;
; I/O pins ; 17 ;
; Maximum fan-out node ; reset ;
; Maximum fan-out ; 29 ;
; Total fan-out ; 569 ;
; Average fan-out ; 3.23 ;
+-------------------------------+-------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+-----------------------------------------------------------------
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 6 ;
; Number of synthesis-generated cells ; 153 ;
; Number of WYSIWYG LUTs ; 6 ;
; Number of synthesis-generated LUTs ; 149 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 39 ;
; Number of cells with combinational logic only ; 120 ;
; Number of cells with registers only ; 4 ;
; Number of cells with combinational logic and registers ; 35 ;
+--------------------------------------------------------+-------+
+----------------------------------------------+
; General Register Statistics ;
+-----------------------------------------------
; Statistic ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR ; 0 ;
; Number of registers using SLOAD ; 0 ;
; Number of registers using ACLR ; 27 ;
; Number of registers using ALOAD ; 0 ;
; Number of registers using CLK_ENABLE ; 36 ;
; Number of registers using OE ; 0 ;
; Number of registers using PRESET ; 0 ;
+--------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Tue Dec 02 20:48:16 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off stopwatch -c stopwatch
Info: Found 2 design units and 1 entities in source file act.vhd
Info: Found design unit 1: act-fun
Info: Found entity 1: act
Info: Found 2 design units and 1 entities in source file minute.vhd
Info: Found design unit 1: minute-fun
Info: Found entity 1: minute
Info: Found 2 design units and 1 entities in source file msecond.vhd
Info: Found design unit 1: msecond-fun
Info: Found entity 1: msecond
Info: Found 2 design units and 1 entities in source file second.vhd
Info: Found design unit 1: second-fun
Info: Found entity 1: second
Info: Found 2 design units and 1 entities in source file stopwatch.vhd
Info: Found design unit 1: stopwatch-behave
Info: Found entity 1: stopwatch
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Implemented 176 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 13 output pins
Info: Implemented 159 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Dec 02 20:48:24 2008
Info: Elapsed time: 00:00:08
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