stopwatch.tan.qmsg

读取4*4键盘的键值

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk1 selout\[5\] act:u4\|sel\[5\] 12.600 ns register " "Info: Minimum tco from clock clk1 to destination pin selout\[5\] through register act:u4\|sel\[5\] is 12.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk1 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 13; CLK Node = 'clk1'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u4\|sel\[5\] 2 REG LC3_C23 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C23; Fanout = 2; REG Node = 'act:u4\|sel\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.200 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns act:u4\|sel\[5\] 1 REG LC3_C23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C23; Fanout = 2; REG Node = 'act:u4\|sel\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { act:u4|sel[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(5.100 ns) 6.200 ns selout\[5\] 2 PIN Pin_78 0 " "Info: 2: + IC(1.100 ns) + CELL(5.100 ns) = 6.200 ns; Loc. = Pin_78; Fanout = 0; PIN Node = 'selout\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.200 ns" { act:u4|sel[5] selout[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 82.26 % " "Info: Total cell delay = 5.100 ns ( 82.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 17.74 % " "Info: Total interconnect delay = 1.100 ns ( 17.74 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.200 ns" { act:u4|sel[5] selout[5] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.200 ns" { act:u4|sel[5] selout[5] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 20:48:46 2008 " "Info: Processing ended: Tue Dec 02 20:48:46 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}