stopwatch.csf.qmsg

读取4*4键盘的键值

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register second:u2\|count\[0\] register second:u2\|count\[7\] 55.25 MHz 18.1 ns Internal " "Info: Clock clk has Internal fmax of 55.25 MHz between source register second:u2\|count\[0\] and destination register second:u2\|count\[7\] (period= 18.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.500 ns + Longest register register " "Info: + Longest register to register delay is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second:u2\|count\[0\] 1 REG LC1_C15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 5; REG Node = 'second:u2\|count\[0\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { second:u2|count[0] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.200 ns) 3.500 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC1_C13 2 " "Info: 2: + IC(2.300 ns) + CELL(1.200 ns) = 3.500 ns; Loc. = LC1_C13; Fanout = 2; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "3.500 ns" { second:u2|count[0] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.800 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC2_C13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC2_C13; Fanout = 2; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "0.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[0] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.100 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC3_C13 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC3_C13; Fanout = 2; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "0.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.400 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC4_C13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC4_C13; Fanout = 2; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "0.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.700 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC5_C13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC5_C13; Fanout = 2; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "0.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.000 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC6_C13 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC6_C13; Fanout = 2; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "0.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.300 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC7_C13 1 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 5.300 ns; Loc. = LC7_C13; Fanout = 1; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "0.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 6.600 ns second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|unreg_res_node\[7\] 9 COMB LC8_C13 1 " "Info: 9: + IC(0.000 ns) + CELL(1.300 ns) = 6.600 ns; Loc. = LC8_C13; Fanout = 1; COMB Node = 'second:u2\|lpm_add_sub:i_rtl_4\|addcore:adder\|unreg_res_node\[7\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "1.300 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|unreg_res_node[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/addcore.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 11.100 ns second:u2\|i53~170 10 COMB LC1_C14 1 " "Info: 10: + IC(2.200 ns) + CELL(2.300 ns) = 11.100 ns; Loc. = LC1_C14; Fanout = 1; COMB Node = 'second:u2\|i53~170'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "4.500 ns" { second:u2|lpm_add_sub:i_rtl_4|addcore:adder|unreg_res_node[7] second:u2|i53~170 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 14.500 ns second:u2\|count\[7\] 11 REG LC2_C15 5 " "Info: 11: + IC(2.200 ns) + CELL(1.200 ns) = 14.500 ns; Loc. = LC2_C15; Fanout = 5; REG Node = 'second:u2\|count\[7\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "3.400 ns" { second:u2|i53~170 second:u2|count[7] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.800 ns 53.79 % " "Info: Total cell delay = 7.800 ns ( 53.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns 46.21 % " "Info: Total interconnect delay = 6.700 ns ( 46.21 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.500 ns" { second:u2|count[0] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[0] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|unreg_res_node[7] second:u2|i53~170 second:u2|count[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_42 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 9; CLK Node = 'clk'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns msecond:u1\|ensec~reg0 2 REG LC1_B24 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B24; Fanout = 10; REG Node = 'msecond:u1\|ensec~reg0'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "3.600 ns" { clk msecond:u1|ensec~reg0 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/msecond.vhd" "" "" { Text "e:/vdhl试验/stopwatch/msecond.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(0.000 ns) 11.400 ns second:u2\|count\[7\] 3 REG LC2_C15 5 " "Info: 3: + IC(5.000 ns) + CELL(0.000 ns) = 11.400 ns; Loc. = LC2_C15; Fanout = 5; REG Node = 'second:u2\|count\[7\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.000 ns" { msecond:u1|ensec~reg0 second:u2|count[7] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 34.21 % " "Info: Total cell delay = 3.900 ns ( 34.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 65.79 % " "Info: Total interconnect delay = 7.500 ns ( 65.79 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "11.400 ns" { clk msecond:u1|ensec~reg0 second:u2|count[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.400 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_42 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 9; CLK Node = 'clk'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns msecond:u1\|ensec~reg0 2 REG LC1_B24 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B24; Fanout = 10; REG Node = 'msecond:u1\|ensec~reg0'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "3.600 ns" { clk msecond:u1|ensec~reg0 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/msecond.vhd" "" "" { Text "e:/vdhl试验/stopwatch/msecond.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(0.000 ns) 11.400 ns second:u2\|count\[0\] 3 REG LC1_C15 5 " "Info: 3: + IC(5.000 ns) + CELL(0.000 ns) = 11.400 ns; Loc. = LC1_C15; Fanout = 5; REG Node = 'second:u2\|count\[0\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.000 ns" { msecond:u1|ensec~reg0 second:u2|count[0] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 34.21 % " "Info: Total cell delay = 3.900 ns ( 34.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 65.79 % " "Info: Total interconnect delay = 7.500 ns ( 65.79 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "11.400 ns" { clk msecond:u1|ensec~reg0 second:u2|count[0] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "11.400 ns" { clk msecond:u1|ensec~reg0 second:u2|count[7] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "11.400 ns" { clk msecond:u1|ensec~reg0 second:u2|count[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.500 ns" { second:u2|count[0] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[0] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] second:u2|lpm_add_sub:i_rtl_4|addcore:adder|unreg_res_node[7] second:u2|i53~170 second:u2|count[7] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "11.400 ns" { clk msecond:u1|ensec~reg0 second:u2|count[7] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "11.400 ns" { clk msecond:u1|ensec~reg0 second:u2|count[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "act:u4\|sel\[5\] reset clk1 11.300 ns register " "Info: tsu for register act:u4\|sel\[5\] (data pin = reset, clock pin = clk1) is 11.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.100 ns + Longest pin register " "Info: + Longest pin to register delay is 14.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns reset 1 PIN Pin_3 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = Pin_3; Fanout = 2; PIN Node = 'reset'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { reset } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.800 ns) 8.900 ns act:u4\|sel\[5\]~31 2 COMB LC1_C1 10 " "Info: 2: + IC(3.600 ns) + CELL(1.800 ns) = 8.900 ns; Loc. = LC1_C1; Fanout = 10; COMB Node = 'act:u4\|sel\[5\]~31'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.400 ns" { reset act:u4|sel[5]~31 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(1.200 ns) 14.100 ns act:u4\|sel\[5\] 3 REG LC3_C23 2 " "Info: 3: + IC(4.000 ns) + CELL(1.200 ns) = 14.100 ns; Loc. = LC3_C23; Fanout = 2; REG Node = 'act:u4\|sel\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.200 ns" { act:u4|sel[5]~31 act:u4|sel[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns 46.10 % " "Info: Total cell delay = 6.500 ns ( 46.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns 53.90 % " "Info: Total interconnect delay = 7.600 ns ( 53.90 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.100 ns" { reset act:u4|sel[5]~31 act:u4|sel[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock clk1 to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 13; CLK Node = 'clk1'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u4\|sel\[5\] 2 REG LC3_C23 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C23; Fanout = 2; REG Node = 'act:u4\|sel\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.100 ns" { reset act:u4|sel[5]~31 act:u4|sel[5] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 led\[2\] act:u4\|num\[1\] 22.900 ns register " "Info: tco from clock clk1 to destination pin led\[2\] through register act:u4\|num\[1\] is 22.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 5.300 ns + Longest register " "Info: + Longest clock path from clock clk1 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 13; CLK Node = 'clk1'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u4\|num\[1\] 2 REG LC2_C8 12 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_C8; Fanout = 12; REG Node = 'act:u4\|num\[1\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u4|num[1] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|num[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.500 ns + Longest register pin " "Info: + Longest register to pin delay is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns act:u4\|num\[1\] 1 REG LC2_C8 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C8; Fanout = 12; REG Node = 'act:u4\|num\[1\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { act:u4|num[1] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.300 ns) 5.700 ns act:u4\|i202~123 2 COMB LC4_A2 2 " "Info: 2: + IC(3.400 ns) + CELL(2.300 ns) = 5.700 ns; Loc. = LC4_A2; Fanout = 2; COMB Node = 'act:u4\|i202~123'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.700 ns" { act:u4|num[1] act:u4|i202~123 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 69 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.800 ns) 9.800 ns act:u4\|daout1\[2\]~4 3 COMB LC5_A8 2 " "Info: 3: + IC(2.300 ns) + CELL(1.800 ns) = 9.800 ns; Loc. = LC5_A8; Fanout = 2; COMB Node = 'act:u4\|daout1\[2\]~4'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "4.100 ns" { act:u4|i202~123 act:u4|daout1[2]~4 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(5.100 ns) 16.500 ns led\[2\] 4 PIN Pin_18 0 " "Info: 4: + IC(1.600 ns) + CELL(5.100 ns) = 16.500 ns; Loc. = Pin_18; Fanout = 0; PIN Node = 'led\[2\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.700 ns" { act:u4|daout1[2]~4 led[2] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns 55.76 % " "Info: Total cell delay = 9.200 ns ( 55.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns 44.24 % " "Info: Total interconnect delay = 7.300 ns ( 44.24 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "16.500 ns" { act:u4|num[1] act:u4|i202~123 act:u4|daout1[2]~4 led[2] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|num[1] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "16.500 ns" { act:u4|num[1] act:u4|i202~123 act:u4|daout1[2]~4 led[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "minute:u3\|count\[6\] set clk 2.500 ns register " "Info: th for register minute:u3\|count\[6\] (data pin = set, clock pin = clk) is 2.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.000 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_42 9 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_42; Fanout = 9; CLK Node = 'clk'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns msecond:u1\|ensec~reg0 2 REG LC1_B24 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B24; Fanout = 10; REG Node = 'msecond:u1\|ensec~reg0'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "3.600 ns" { clk msecond:u1|ensec~reg0 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/msecond.vhd" "" "" { Text "e:/vdhl试验/stopwatch/msecond.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.000 ns) + CELL(1.100 ns) 12.500 ns second:u2\|enmin~reg0 3 REG LC5_C16 9 " "Info: 3: + IC(5.000 ns) + CELL(1.100 ns) = 12.500 ns; Loc. = LC5_C16; Fanout = 9; REG Node = 'second:u2\|enmin~reg0'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.100 ns" { msecond:u1|ensec~reg0 second:u2|enmin~reg0 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 15.000 ns minute:u3\|count\[6\] 4 REG LC5_C20 7 " "Info: 4: + IC(2.500 ns) + CELL(0.000 ns) = 15.000 ns; Loc. = LC5_C20; Fanout = 7; REG Node = 'minute:u3\|count\[6\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { second:u2|enmin~reg0 minute:u3|count[6] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/minute.vhd" "" "" { Text "E:/vdhl试验/stopwatch/minute.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 33.33 % " "Info: Total cell delay = 5.000 ns ( 33.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.000 ns 66.67 % " "Info: Total interconnect delay = 10.000 ns ( 66.67 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "15.000 ns" { clk msecond:u1|ensec~reg0 second:u2|enmin~reg0 minute:u3|count[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "E:/vdhl试验/stopwatch/minute.vhd" "" "" { Text "E:/vdhl试验/stopwatch/minute.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 14.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns set 1 PIN Pin_5 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = Pin_5; Fanout = 2; PIN Node = 'set'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { set } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(1.800 ns) 9.300 ns msecond:u1\|count\[6\]~172 2 COMB LC2_B24 24 " "Info: 2: + IC(4.000 ns) + CELL(1.800 ns) = 9.300 ns; Loc. = LC2_B24; Fanout = 24; COMB Node = 'msecond:u1\|count\[6\]~172'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.800 ns" { set msecond:u1|count[6]~172 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/msecond.vhd" "" "" { Text "e:/vdhl试验/stopwatch/msecond.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.200 ns) 14.100 ns minute:u3\|count\[6\] 3 REG LC5_C20 7 " "Info: 3: + IC(3.600 ns) + CELL(1.200 ns) = 14.100 ns; Loc. = LC5_C20; Fanout = 7; REG Node = 'minute:u3\|count\[6\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "4.800 ns" { msecond:u1|count[6]~172 minute:u3|count[6] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/minute.vhd" "" "" { Text "E:/vdhl试验/stopwatch/minute.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.500 ns 46.10 % " "Info: Total cell delay = 6.500 ns ( 46.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns 53.90 % " "Info: Total interconnect delay = 7.600 ns ( 53.90 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.100 ns" { set msecond:u1|count[6]~172 minute:u3|count[6] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "15.000 ns" { clk msecond:u1|ensec~reg0 second:u2|enmin~reg0 minute:u3|count[6] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.100 ns" { set msecond:u1|count[6]~172 minute:u3|count[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk1 selout\[5\] act:u4\|sel\[5\] 12.600 ns register " "Info: Minimum tco from clock clk1 to destination pin selout\[5\] through register act:u4\|sel\[5\] is 12.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk1 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 13; CLK Node = 'clk1'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u4\|sel\[5\] 2 REG LC3_C23 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C23; Fanout = 2; REG Node = 'act:u4\|sel\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.200 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns act:u4\|sel\[5\] 1 REG LC3_C23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C23; Fanout = 2; REG Node = 'act:u4\|sel\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { act:u4|sel[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(5.100 ns) 6.200 ns selout\[5\] 2 PIN Pin_78 0 " "Info: 2: + IC(1.100 ns) + CELL(5.100 ns) = 6.200 ns; Loc. = Pin_78; Fanout = 0; PIN Node = 'selout\[5\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.200 ns" { act:u4|sel[5] selout[5] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns 82.26 % " "Info: Total cell delay = 5.100 ns ( 82.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 17.74 % " "Info: Total interconnect delay = 1.100 ns ( 17.74 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.200 ns" { act:u4|sel[5] selout[5] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|sel[5] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "6.200 ns" { act:u4|sel[5] selout[5] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 20:48:46 2008 " "Info: Processing ended: Tue Dec 02 20:48:46 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" {  } {  } 0}