stopwatch.csf.qmsg

读取4*4键盘的键值

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off stopwatch -c stopwatch " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off stopwatch -c stopwatch" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 20:48:44 2008 " "Info: Processing ended: Tue Dec 02 20:48:44 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 20:48:45 2008 " "Info: Processing started: Tue Dec 02 20:48:45 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off stopwatch -c stopwatch " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off stopwatch -c stopwatch" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node clk1 is an undefined clock" {  } { { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "second:u2\|enmin~reg0 " "Info: Detected ripple clock second:u2\|enmin~reg0 as buffer" {  } { { "e:/vdhl试验/stopwatch/second.vhd" "" "" { Text "e:/vdhl试验/stopwatch/second.vhd" 20 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "second:u2\|enmin~reg0" } } } }  } 0} { "Info" "ITDB_RIPPLE_CLK" "msecond:u1\|ensec~reg0 " "Info: Detected ripple clock msecond:u1\|ensec~reg0 as buffer" {  } { { "e:/vdhl试验/stopwatch/msecond.vhd" "" "" { Text "e:/vdhl试验/stopwatch/msecond.vhd" 22 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "msecond:u1\|ensec~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register act:u4\|count\[0\] register act:u4\|num\[2\] 55.87 MHz 17.9 ns Internal " "Info: Clock clk1 has Internal fmax of 55.87 MHz between source register act:u4\|count\[0\] and destination register act:u4\|num\[2\] (period= 17.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest register register " "Info: + Longest register to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns act:u4\|count\[0\] 1 REG LC1_C8 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C8; Fanout = 26; REG Node = 'act:u4\|count\[0\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { act:u4|count[0] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(2.300 ns) 4.800 ns act:u4\|i68~443 2 COMB LC2_C9 1 " "Info: 2: + IC(2.500 ns) + CELL(2.300 ns) = 4.800 ns; Loc. = LC2_C9; Fanout = 1; COMB Node = 'act:u4\|i68~443'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "4.800 ns" { act:u4|count[0] act:u4|i68~443 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 7.200 ns act:u4\|i68~444 3 COMB LC3_C9 1 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 7.200 ns; Loc. = LC3_C9; Fanout = 1; COMB Node = 'act:u4\|i68~444'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.400 ns" { act:u4|i68~443 act:u4|i68~444 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 9.600 ns act:u4\|i68~445 4 COMB LC6_C9 1 " "Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 9.600 ns; Loc. = LC6_C9; Fanout = 1; COMB Node = 'act:u4\|i68~445'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.400 ns" { act:u4|i68~444 act:u4|i68~445 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 12.000 ns act:u4\|i68~446 5 COMB LC7_C9 1 " "Info: 5: + IC(0.600 ns) + CELL(1.800 ns) = 12.000 ns; Loc. = LC7_C9; Fanout = 1; COMB Node = 'act:u4\|i68~446'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.400 ns" { act:u4|i68~445 act:u4|i68~446 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 43 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 14.300 ns act:u4\|num\[2\] 6 REG LC1_C9 13 " "Info: 6: + IC(0.600 ns) + CELL(1.700 ns) = 14.300 ns; Loc. = LC1_C9; Fanout = 13; REG Node = 'act:u4\|num\[2\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.300 ns" { act:u4|i68~446 act:u4|num[2] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.400 ns 65.73 % " "Info: Total cell delay = 9.400 ns ( 65.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns 34.27 % " "Info: Total interconnect delay = 4.900 ns ( 34.27 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.300 ns" { act:u4|count[0] act:u4|i68~443 act:u4|i68~444 act:u4|i68~445 act:u4|i68~446 act:u4|num[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk1 to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 13; CLK Node = 'clk1'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u4\|num\[2\] 2 REG LC1_C9 13 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C9; Fanout = 13; REG Node = 'act:u4\|num\[2\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u4|num[2] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|num[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 5.300 ns - Longest register " "Info: - Longest clock path from clock clk1 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 13 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 13; CLK Node = 'clk1'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/stopwatch.vhd" "" "" { Text "e:/vdhl试验/stopwatch/stopwatch.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u4\|count\[0\] 2 REG LC1_C8 26 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C8; Fanout = 26; REG Node = 'act:u4\|count\[0\]'" {  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u4|count[0] } "NODE_NAME" } } } { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|count[0] } "NODE_NAME" } } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|num[2] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|count[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "e:/vdhl试验/stopwatch/act.vhd" "" "" { Text "e:/vdhl试验/stopwatch/act.vhd" 24 -1 0 } }  } 0}  } { { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "14.300 ns" { act:u4|count[0] act:u4|i68~443 act:u4|i68~444 act:u4|i68~445 act:u4|i68~446 act:u4|num[2] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|num[2] } "NODE_NAME" } } } { "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" "" "" { Report "E:/vdhl试验/stopwatch/db/stopwatch_cmp.qrpt" Compiler "stopwatch" "UNKNOWN" "V1" "E:/vdhl试验/stopwatch/db/stopwatch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u4|count[0] } "NODE_NAME" } } }  } 0}