stopwatch.vhd

读取4*4键盘的键值

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stopwatch is
port(clk,clk1: in std_logic;
   reset: in std_logic;
     set: in std_logic;
     selout: out std_logic_vector( 5 downto 0);
     led: out   std_logic_vector(6 downto 0));
end entity stopwatch;

architecture behave of stopwatch is
component msecond is
port(
		clk, reset,set    : in	std_logic;
		ensec             : out	std_logic;
		daout             : out  std_logic_vector (7 downto 0));
end component msecond ;

component second is
port(
		clk, reset ,set    : in std_logic;
		enmin              : out std_logic;
		daout              : out std_logic_vector (7 downto 0));
end component  second ;

component  minute is
port(
		clk, reset ,set     : in  std_logic;
		daout               : out std_logic_vector (7 downto 0));
end component  minute;

component act is
port(
		clk, clr: in std_logic;
		second,minute,hour : in  std_logic_vector (7 downto 0);
		daout1   : out  std_logic_vector( 6 downto 0);
		sel1       : out  std_logic_vector( 5 downto 0));
end component act;

signal ensec,enmin :std_logic;
signal sel :std_logic_vector(2 downto 0);
signal daout1     :std_logic_vector(7 downto 0);
signal daout2,daout3:std_logic_vector(7 downto 0);
signal num:std_logic_vector(3 downto 0);
begin
u1: msecond port map (clk,reset,set,ensec,daout1);
u2: second  port map (ensec,reset,set,enmin,daout2);
u3: minute  port map (enmin,reset,set,daout3);
u4: act     port map (clk1,reset,daout1,daout2,daout3,led,selout);


end architecture behave;