qudou.vhd
来自「通用的基于状态机的VHDL按键及信号去抖动模块」· VHDL 代码 · 共 86 行
VHD
86 行
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:41:28 01/25/2008
-- Design Name:
-- Module Name: qudou - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity qudou is
port(clkin: IN STD_LOGIC ;
reset: IN STD_LOGIC ;
din: IN STD_LOGIC ;
dout: OUT STD_LOGIC);
end qudou;
architecture Behavioral of qudou is
TYPE state IS( s0,s1,s2,s3);
SIGNAL pre_s, next_s: state;
begin
P0:PROCESS(reset, clkin)
BEGIN
if reset = '0' then
pre_s <= s0;
elsif rising_edge(clkin) then
pre_s <= next_s;
else
null;
end if;
END PROCESS P0;
P1:PROCESS( pre_s, next_s, din )
BEGIN
case pre_s is
when s0 =>
dout <= '1';
if din = '1' then
next_s <= s0;
else
next_s <= s1;
end if;
when s1 =>
dout <= '1';
if din = '1' then
next_s <= s0;
else
next_s <= s2;
end if;
when s2 =>
dout <= '1';
if din = '1' then
next_s <= s0;
else
next_s <= s3;
end if;
when s3 =>
dout <= '0';
if din = '1' then
next_s <= s0;
else
next_s <= s1;
end if;
end case;
END PROCESS P1;
end Behavioral;
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