📄 compare.tan.rpt
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Timing Analyzer report for compare
Tue Dec 16 20:02:48 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.722 ns ; d[5] ; f0[5] ; -- ; ok ; 0 ;
; Worst-case tco ; N/A ; None ; 7.019 ns ; f0[5] ; f[5] ; ok ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.989 ns ; e[3] ; g0 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; ok ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-------+----------+
; N/A ; None ; 5.722 ns ; d[5] ; f0[5] ; ok ;
; N/A ; None ; 5.455 ns ; d[5] ; g0 ; clk ;
; N/A ; None ; 5.345 ns ; d[4] ; f0[4] ; ok ;
; N/A ; None ; 5.311 ns ; d[3] ; g0 ; clk ;
; N/A ; None ; 5.311 ns ; d[3] ; f0[3] ; ok ;
; N/A ; None ; 5.222 ns ; d[4] ; g0 ; clk ;
; N/A ; None ; 5.144 ns ; d[2] ; f0[2] ; ok ;
; N/A ; None ; 5.118 ns ; e[5] ; g0 ; clk ;
; N/A ; None ; 5.014 ns ; d[1] ; f0[1] ; ok ;
; N/A ; None ; 4.989 ns ; d[2] ; g0 ; clk ;
; N/A ; None ; 4.927 ns ; e[2] ; g0 ; clk ;
; N/A ; None ; 4.847 ns ; e[0] ; g0 ; clk ;
; N/A ; None ; 4.716 ns ; e[1] ; g0 ; clk ;
; N/A ; None ; 4.641 ns ; e[4] ; g0 ; clk ;
; N/A ; None ; 4.628 ns ; d[0] ; f0[0] ; ok ;
; N/A ; None ; 4.572 ns ; d[1] ; g0 ; clk ;
; N/A ; None ; 3.706 ns ; d[0] ; g0 ; clk ;
; N/A ; None ; 1.041 ns ; e[3] ; g0 ; clk ;
+-------+--------------+------------+------+-------+----------+
+---------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+------+------------+
; N/A ; None ; 7.019 ns ; f0[5] ; f[5] ; ok ;
; N/A ; None ; 6.822 ns ; f0[0] ; f[0] ; ok ;
; N/A ; None ; 6.727 ns ; g0 ; g ; clk ;
; N/A ; None ; 6.703 ns ; f0[1] ; f[1] ; ok ;
; N/A ; None ; 6.540 ns ; f0[2] ; f[2] ; ok ;
; N/A ; None ; 6.534 ns ; f0[3] ; f[3] ; ok ;
; N/A ; None ; 6.532 ns ; f0[4] ; f[4] ; ok ;
+-------+--------------+------------+-------+------+------------+
+-------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A ; None ; -0.989 ns ; e[3] ; g0 ; clk ;
; N/A ; None ; -3.654 ns ; d[0] ; g0 ; clk ;
; N/A ; None ; -3.779 ns ; d[0] ; f0[0] ; ok ;
; N/A ; None ; -4.162 ns ; d[1] ; f0[1] ; ok ;
; N/A ; None ; -4.292 ns ; d[2] ; f0[2] ; ok ;
; N/A ; None ; -4.378 ns ; d[4] ; f0[4] ; ok ;
; N/A ; None ; -4.460 ns ; d[3] ; f0[3] ; ok ;
; N/A ; None ; -4.520 ns ; d[1] ; g0 ; clk ;
; N/A ; None ; -4.589 ns ; e[4] ; g0 ; clk ;
; N/A ; None ; -4.664 ns ; e[1] ; g0 ; clk ;
; N/A ; None ; -4.756 ns ; d[5] ; f0[5] ; ok ;
; N/A ; None ; -4.795 ns ; e[0] ; g0 ; clk ;
; N/A ; None ; -4.875 ns ; e[2] ; g0 ; clk ;
; N/A ; None ; -4.937 ns ; d[2] ; g0 ; clk ;
; N/A ; None ; -5.066 ns ; e[5] ; g0 ; clk ;
; N/A ; None ; -5.170 ns ; d[4] ; g0 ; clk ;
; N/A ; None ; -5.259 ns ; d[3] ; g0 ; clk ;
; N/A ; None ; -5.403 ns ; d[5] ; g0 ; clk ;
+---------------+-------------+-----------+------+-------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Dec 16 20:02:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off compare -c compare --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "f0[0]" is a latch
Warning: Node "f0[1]" is a latch
Warning: Node "f0[2]" is a latch
Warning: Node "f0[3]" is a latch
Warning: Node "f0[4]" is a latch
Warning: Node "f0[5]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Assuming node "ok" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "f0[5]" (data pin = "d[5]", clock pin = "ok") is 5.722 ns
Info: + Longest pin to register delay is 7.638 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_69; Fanout = 2; PIN Node = 'd[5]'
Info: 2: + IC(5.871 ns) + CELL(0.292 ns) = 7.638 ns; Loc. = LC_X26_Y8_N0; Fanout = 1; REG Node = 'f0[5]'
Info: Total cell delay = 1.767 ns ( 23.13 % )
Info: Total interconnect delay = 5.871 ns ( 76.87 % )
Info: + Micro setup delay of destination is 0.966 ns
Info: - Shortest clock path from clock "ok" to destination register is 2.882 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'ok'
Info: 2: + IC(1.299 ns) + CELL(0.114 ns) = 2.882 ns; Loc. = LC_X26_Y8_N0; Fanout = 1; REG Node = 'f0[5]'
Info: Total cell delay = 1.583 ns ( 54.93 % )
Info: Total interconnect delay = 1.299 ns ( 45.07 % )
Info: tco from clock "ok" to destination pin "f[5]" through register "f0[5]" is 7.019 ns
Info: + Longest clock path from clock "ok" to source register is 2.882 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 6; CLK Node = 'ok'
Info: 2: + IC(1.299 ns) + CELL(0.114 ns) = 2.882 ns; Loc. = LC_X26_Y8_N0; Fanout = 1; REG Node = 'f0[5]'
Info: Total cell delay = 1.583 ns ( 54.93 % )
Info: Total interconnect delay = 1.299 ns ( 45.07 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Longest register to pin delay is 4.137 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y8_N0; Fanout = 1; REG Node = 'f0[5]'
Info: 2: + IC(2.029 ns) + CELL(2.108 ns) = 4.137 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'f[5]'
Info: Total cell delay = 2.108 ns ( 50.95 % )
Info: Total interconnect delay = 2.029 ns ( 49.05 % )
Info: th for register "g0" (data pin = "e[3]", clock pin = "clk") is -0.989 ns
Info: + Longest clock path from clock "clk" to destination register is 3.238 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.058 ns) + CELL(0.711 ns) = 3.238 ns; Loc. = LC_X26_Y8_N4; Fanout = 1; REG Node = 'g0'
Info: Total cell delay = 2.180 ns ( 67.33 % )
Info: Total interconnect delay = 1.058 ns ( 32.67 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 4.242 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'e[3]'
Info: 2: + IC(1.016 ns) + CELL(0.590 ns) = 3.075 ns; Loc. = LC_X26_Y8_N6; Fanout = 1; COMB Node = 'Equal0~55'
Info: 3: + IC(0.429 ns) + CELL(0.738 ns) = 4.242 ns; Loc. = LC_X26_Y8_N4; Fanout = 1; REG Node = 'g0'
Info: Total cell delay = 2.797 ns ( 65.94 % )
Info: Total interconnect delay = 1.445 ns ( 34.06 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings
Info: Processing ended: Tue Dec 16 20:02:48 2008
Info: Elapsed time: 00:00:01
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