clock.tan.qmsg

4位二进制密码锁,可能会对别人有点帮助,大家下来看看把

{ "Info" "ITDB_FULL_TPD_RESULT" "aa\[2\] mm\[2\] 12.465 ns Longest " "Info: Longest tpd from source pin \"aa\[2\]\" to destination pin \"mm\[2\]\" is 12.465 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns aa\[2\] 1 PIN PIN_62 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_62; Fanout = 3; PIN Node = 'aa\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { aa[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.004 ns) + CELL(0.292 ns) 7.771 ns input:u1\|comb~164 2 COMB LC_X21_Y12_N1 1 " "Info: 2: + IC(6.004 ns) + CELL(0.292 ns) = 7.771 ns; Loc. = LC_X21_Y12_N1; Fanout = 1; COMB Node = 'input:u1\|comb~164'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.296 ns" { aa[2] input:u1|comb~164 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.570 ns) + CELL(2.124 ns) 12.465 ns mm\[2\] 3 PIN PIN_85 0 " "Info: 3: + IC(2.570 ns) + CELL(2.124 ns) = 12.465 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'mm\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.694 ns" { input:u1|comb~164 mm[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.891 ns ( 31.22 % ) " "Info: Total cell delay = 3.891 ns ( 31.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.574 ns ( 68.78 % ) " "Info: Total interconnect delay = 8.574 ns ( 68.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.465 ns" { aa[2] input:u1|comb~164 mm[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.465 ns" { aa[2] aa[2]~out0 input:u1|comb~164 mm[2] } { 0.000ns 0.000ns 6.004ns 2.570ns } { 0.000ns 1.475ns 0.292ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "compare:u2\|f0\[0\] aa\[0\] okk -4.150 ns register " "Info: th for register \"compare:u2\|f0\[0\]\" (data pin = \"aa\[0\]\", clock pin = \"okk\") is -4.150 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "okk destination 2.791 ns + Longest register " "Info: + Longest clock path from clock \"okk\" to destination register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns okk 1 CLK PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'okk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { okk } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(0.114 ns) 2.791 ns compare:u2\|f0\[0\] 2 REG LC_X20_Y12_N2 1 " "Info: 2: + IC(1.208 ns) + CELL(0.114 ns) = 2.791 ns; Loc. = LC_X20_Y12_N2; Fanout = 1; REG Node = 'compare:u2\|f0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.322 ns" { okk compare:u2|f0[0] } "NODE_NAME" } } { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 56.72 % ) " "Info: Total cell delay = 1.583 ns ( 56.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.208 ns ( 43.28 % ) " "Info: Total interconnect delay = 1.208 ns ( 43.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.791 ns" { okk compare:u2|f0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.791 ns" { okk okk~out0 compare:u2|f0[0] } { 0.000ns 0.000ns 1.208ns } { 0.000ns 1.469ns 0.114ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.941 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns aa\[0\] 1 PIN PIN_119 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_119; Fanout = 3; PIN Node = 'aa\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { aa[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/clock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.024 ns) + CELL(0.442 ns) 6.941 ns compare:u2\|f0\[0\] 2 REG LC_X20_Y12_N2 1 " "Info: 2: + IC(5.024 ns) + CELL(0.442 ns) = 6.941 ns; Loc. = LC_X20_Y12_N2; Fanout = 1; REG Node = 'compare:u2\|f0\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.466 ns" { aa[0] compare:u2|f0[0] } "NODE_NAME" } } { "compare.vhd" "" { Text "C:/Documents and Settings/user/桌面/suo/compare.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.917 ns ( 27.62 % ) " "Info: Total cell delay = 1.917 ns ( 27.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.024 ns ( 72.38 % ) " "Info: Total interconnect delay = 5.024 ns ( 72.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.941 ns" { aa[0] compare:u2|f0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.941 ns" { aa[0] aa[0]~out0 compare:u2|f0[0] } { 0.000ns 0.000ns 5.024ns } { 0.000ns 1.475ns 0.442ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.791 ns" { okk compare:u2|f0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.791 ns" { okk okk~out0 compare:u2|f0[0] } { 0.000ns 0.000ns 1.208ns } { 0.000ns 1.469ns 0.114ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.941 ns" { aa[0] compare:u2|f0[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.941 ns" { aa[0] aa[0]~out0 compare:u2|f0[0] } { 0.000ns 0.000ns 5.024ns } { 0.000ns 1.475ns 0.442ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 8 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 16 20:22:31 2008 " "Info: Processing ended: Tue Dec 16 20:22:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}