clock.tan.rpt

4位二进制密码锁,可能会对别人有点帮助,大家下来看看把

+-------+--------------+------------+---------------+----+------------+


+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+-------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To    ;
+-------+-------------------+-----------------+-------+-------+
; N/A   ; None              ; 12.465 ns       ; aa[2] ; mm[2] ;
; N/A   ; None              ; 11.870 ns       ; bb[2] ; nn[2] ;
; N/A   ; None              ; 11.792 ns       ; aa[1] ; mm[1] ;
; N/A   ; None              ; 11.445 ns       ; enen  ; mm[2] ;
; N/A   ; None              ; 11.442 ns       ; enen  ; mm[1] ;
; N/A   ; None              ; 11.125 ns       ; aa[0] ; mm[0] ;
; N/A   ; None              ; 10.996 ns       ; enen  ; mm[0] ;
; N/A   ; None              ; 10.978 ns       ; enen  ; nn[2] ;
; N/A   ; None              ; 10.914 ns       ; bb[1] ; nn[1] ;
; N/A   ; None              ; 10.465 ns       ; enen  ; nn[1] ;
; N/A   ; None              ; 10.385 ns       ; bb[0] ; nn[0] ;
; N/A   ; None              ; 10.151 ns       ; enen  ; nn[0] ;
+-------+-------------------+-----------------+-------+-------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+-------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To               ; To Clock ;
+---------------+-------------+-----------+-------+------------------+----------+
; N/A           ; None        ; -4.150 ns ; aa[0] ; compare:u2|f0[0] ; okk      ;
; N/A           ; None        ; -4.225 ns ; bb[0] ; compare:u2|f0[3] ; okk      ;
; N/A           ; None        ; -4.605 ns ; aa[1] ; compare:u2|f0[1] ; okk      ;
; N/A           ; None        ; -4.619 ns ; bb[1] ; compare:u2|f0[4] ; okk      ;
; N/A           ; None        ; -4.635 ns ; aa[0] ; compare:u2|g0    ; clkk     ;
; N/A           ; None        ; -4.853 ns ; bb[2] ; compare:u2|f0[5] ; okk      ;
; N/A           ; None        ; -4.993 ns ; aa[2] ; compare:u2|f0[2] ; okk      ;
; N/A           ; None        ; -5.160 ns ; bb[0] ; compare:u2|g0    ; clkk     ;
; N/A           ; None        ; -5.391 ns ; aa[1] ; compare:u2|g0    ; clkk     ;
; N/A           ; None        ; -5.548 ns ; bb[1] ; compare:u2|g0    ; clkk     ;
; N/A           ; None        ; -5.997 ns ; bb[2] ; compare:u2|g0    ; clkk     ;
; N/A           ; None        ; -6.081 ns ; aa[2] ; compare:u2|g0    ; clkk     ;
+---------------+-------------+-----------+-------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Dec 16 20:22:30 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "compare:u2|f0[2]" is a latch
    Warning: Node "compare:u2|f0[5]" is a latch
    Warning: Node "compare:u2|f0[0]" is a latch
    Warning: Node "compare:u2|f0[1]" is a latch
    Warning: Node "compare:u2|f0[4]" is a latch
    Warning: Node "compare:u2|f0[3]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkk" is an undefined clock
    Info: Assuming node "okk" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Clock "clkk" Internal fmax is restricted to 275.03 MHz between source register "flip:u3|m0[2]" and destination register "compare:u2|g0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.655 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N1; Fanout = 1; REG Node = 'flip:u3|m0[2]'
            Info: 2: + IC(0.517 ns) + CELL(0.114 ns) = 0.631 ns; Loc. = LC_X20_Y12_N8; Fanout = 1; COMB Node = 'compare:u2|Equal0~53'
            Info: 3: + IC(0.417 ns) + CELL(0.607 ns) = 1.655 ns; Loc. = LC_X20_Y12_N7; Fanout = 3; REG Node = 'compare:u2|g0'
            Info: Total cell delay = 0.721 ns ( 43.56 % )
            Info: Total interconnect delay = 0.934 ns ( 56.44 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clkk" to destination register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clkk'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y12_N7; Fanout = 3; REG Node = 'compare:u2|g0'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
            Info: - Longest clock path from clock "clkk" to source register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clkk'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y12_N1; Fanout = 1; REG Node = 'flip:u3|m0[2]'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "compare:u2|g0" (data pin = "aa[2]", clock pin = "clkk") is 6.133 ns
    Info: + Longest pin to register delay is 8.878 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_62; Fanout = 3; PIN Node = 'aa[2]'
        Info: 2: + IC(5.937 ns) + CELL(0.442 ns) = 7.854 ns; Loc. = LC_X20_Y12_N8; Fanout = 1; COMB Node = 'compare:u2|Equal0~53'
        Info: 3: + IC(0.417 ns) + CELL(0.607 ns) = 8.878 ns; Loc. = LC_X20_Y12_N7; Fanout = 3; REG Node = 'compare:u2|g0'
        Info: Total cell delay = 2.524 ns ( 28.43 % )
        Info: Total interconnect delay = 6.354 ns ( 71.57 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clkk" to destination register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clkk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y12_N7; Fanout = 3; REG Node = 'compare:u2|g0'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
Info: tco from clock "clkk" to destination pin "qq" through register "compare:u2|g0" is 9.223 ns
    Info: + Longest clock path from clock "clkk" to source register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clkk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y12_N7; Fanout = 3; REG Node = 'compare:u2|g0'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.217 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N7; Fanout = 3; REG Node = 'compare:u2|g0'
        Info: 2: + IC(4.109 ns) + CELL(2.108 ns) = 6.217 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'qq'
        Info: Total cell delay = 2.108 ns ( 33.91 % )
        Info: Total interconnect delay = 4.109 ns ( 66.09 % )
Info: Longest tpd from source pin "aa[2]" to destination pin "mm[2]" is 12.465 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_62; Fanout = 3; PIN Node = 'aa[2]'
    Info: 2: + IC(6.004 ns) + CELL(0.292 ns) = 7.771 ns; Loc. = LC_X21_Y12_N1; Fanout = 1; COMB Node = 'input:u1|comb~164'
    Info: 3: + IC(2.570 ns) + CELL(2.124 ns) = 12.465 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'mm[2]'
    Info: Total cell delay = 3.891 ns ( 31.22 % )
    Info: Total interconnect delay = 8.574 ns ( 68.78 % )
Info: th for register "compare:u2|f0[0]" (data pin = "aa[0]", clock pin = "okk") is -4.150 ns
    Info: + Longest clock path from clock "okk" to destination register is 2.791 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'okk'
        Info: 2: + IC(1.208 ns) + CELL(0.114 ns) = 2.791 ns; Loc. = LC_X20_Y12_N2; Fanout = 1; REG Node = 'compare:u2|f0[0]'
        Info: Total cell delay = 1.583 ns ( 56.72 % )
        Info: Total interconnect delay = 1.208 ns ( 43.28 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 6.941 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_119; Fanout = 3; PIN Node = 'aa[0]'
        Info: 2: + IC(5.024 ns) + CELL(0.442 ns) = 6.941 ns; Loc. = LC_X20_Y12_N2; Fanout = 1; REG Node = 'compare:u2|f0[0]'
        Info: Total cell delay = 1.917 ns ( 27.62 % )
        Info: Total interconnect delay = 5.024 ns ( 72.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings
    Info: Processing ended: Tue Dec 16 20:22:31 2008
    Info: Elapsed time: 00:00:01