clock.map.rpt

4位二进制密码锁,可能会对别人有点帮助,大家下来看看把

;     -- normal mode                          ; 22    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 6     ;
;                                             ;       ;
; Total registers                             ; 7     ;
; I/O pins                                    ; 19    ;
; Maximum fan-out node                        ; clkk  ;
; Maximum fan-out                             ; 7     ;
; Total fan-out                               ; 73    ;
; Average fan-out                             ; 1.78  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |clock                     ; 22 (0)      ; 7            ; 0           ; 0    ; 19   ; 0            ; 15 (0)       ; 3 (0)             ; 4 (0)            ; 0 (0)           ; 0 (0)      ; |clock              ;
;    |compare:u2|            ; 10 (10)     ; 1            ; 0           ; 0    ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |clock|compare:u2   ;
;    |flip:u3|               ; 6 (6)       ; 6            ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |clock|flip:u3      ;
;    |input:u1|              ; 6 (6)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |clock|input:u1     ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; compare:u2|f0[0]                                   ; okk                 ; yes                    ;
; compare:u2|f0[1]                                   ; okk                 ; yes                    ;
; compare:u2|f0[2]                                   ; okk                 ; yes                    ;
; compare:u2|f0[3]                                   ; okk                 ; yes                    ;
; compare:u2|f0[4]                                   ; okk                 ; yes                    ;
; compare:u2|f0[5]                                   ; okk                 ; yes                    ;
; Number of user-specified and inferred latches = 6  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 7     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; flip:u3|m0[2]                          ; 1       ;
; flip:u3|m0[0]                          ; 1       ;
; flip:u3|m0[1]                          ; 1       ;
; Total number of inverted registers = 3 ;         ;
+----------------------------------------+---------+


+------------------------------------+
; Source assignments for compare:u2  ;
+----------------+-------+------+----+
; Assignment     ; Value ; From ; To ;
+----------------+-------+------+----+
; POWER_UP_LEVEL ; Low   ; -    ; g0 ;
+----------------+-------+------+----+


+---------------------------------------+
; Source assignments for flip:u3        ;
+----------------+-------+------+-------+
; Assignment     ; Value ; From ; To    ;
+----------------+-------+------+-------+
; POWER_UP_LEVEL ; High  ; -    ; m0[0] ;
; POWER_UP_LEVEL ; High  ; -    ; m0[1] ;
; POWER_UP_LEVEL ; High  ; -    ; m0[2] ;
; POWER_UP_LEVEL ; Low   ; -    ; m0[3] ;
; POWER_UP_LEVEL ; Low   ; -    ; m0[4] ;
; POWER_UP_LEVEL ; Low   ; -    ; m0[5] ;
+----------------+-------+------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Dec 16 20:22:20 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file compare.vhd
    Info: Found design unit 1: compare-behave
    Info: Found entity 1: compare
Info: Found 2 design units, including 1 entities, in source file flip.vhd
    Info: Found design unit 1: flip-behave
    Info: Found entity 1: flip
Info: Found 2 design units, including 1 entities, in source file input.vhd
    Info: Found design unit 1: input-behave
    Info: Found entity 1: input
Info: Found 2 design units, including 1 entities, in source file output.vhd
    Info: Found design unit 1: output-behave
    Info: Found entity 1: output
Info: Found 2 design units, including 1 entities, in source file clock.vhd
    Info: Found design unit 1: clock-behave
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Info: Elaborating entity "input" for hierarchy "input:u1"
Warning (10631): VHDL Process Statement warning at input.vhd(14): inferring latch(es) for signal or variable "m0", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at input.vhd(29): inferring latch(es) for signal or variable "n0", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at input.vhd(29): inferred latch for "n0[0]"
Info (10041): Verilog HDL or VHDL info at input.vhd(29): inferred latch for "n0[1]"
Info (10041): Verilog HDL or VHDL info at input.vhd(29): inferred latch for "n0[2]"
Info (10041): Verilog HDL or VHDL info at input.vhd(14): inferred latch for "m0[0]"
Info (10041): Verilog HDL or VHDL info at input.vhd(14): inferred latch for "m0[1]"
Info (10041): Verilog HDL or VHDL info at input.vhd(14): inferred latch for "m0[2]"
Info: Elaborating entity "compare" for hierarchy "compare:u2"
Warning (10492): VHDL Process Statement warning at compare.vhd(26): signal "ok" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at compare.vhd(15): inferring latch(es) for signal or variable "f0", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[0]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[1]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[2]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[3]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[4]"
Info (10041): Verilog HDL or VHDL info at compare.vhd(15): inferred latch for "f0[5]"
Info: Elaborating entity "flip" for hierarchy "flip:u3"
Info: Elaborating entity "output" for hierarchy "output:u4"
Info: Registers with preset signals will power-up high
Info: Implemented 41 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 9 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue Dec 16 20:22:21 2008
    Info: Elapsed time: 00:00:02