control.fit.qmsg

VHDL编写的6层电梯控制器

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "31 unused 3.30 11 20 0 " "Info: Number of I/O pins in group: 31 (unused VREF, 3.30 VCCIO, 11 input, 20 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.405 ns register register " "Info: Estimated most critical path is register to register delay of 4.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns position\[0\] 1 REG LAB_X14_Y12 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y12; Fanout = 17; REG Node = 'position\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { position[0] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.184 ns) + CELL(0.590 ns) 1.774 ns ldown\[5\]~495 2 COMB LAB_X11_Y13 1 " "Info: 2: + IC(1.184 ns) + CELL(0.590 ns) = 1.774 ns; Loc. = LAB_X11_Y13; Fanout = 1; COMB Node = 'ldown\[5\]~495'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.774 ns" { position[0] ldown[5]~495 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 2.438 ns ldown\[5\]~496 3 COMB LAB_X11_Y13 1 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 2.438 ns; Loc. = LAB_X11_Y13; Fanout = 1; COMB Node = 'ldown\[5\]~496'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "0.664 ns" { ldown[5]~495 ldown[5]~496 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.442 ns) 3.102 ns ldown\[5\]~498 4 COMB LAB_X11_Y13 1 " "Info: 4: + IC(0.222 ns) + CELL(0.442 ns) = 3.102 ns; Loc. = LAB_X11_Y13; Fanout = 1; COMB Node = 'ldown\[5\]~498'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "0.664 ns" { ldown[5]~496 ldown[5]~498 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.867 ns) 4.405 ns ldown\[5\] 5 REG LAB_X11_Y13 5 " "Info: 5: + IC(0.436 ns) + CELL(0.867 ns) = 4.405 ns; Loc. = LAB_X11_Y13; Fanout = 5; REG Node = 'ldown\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.303 ns" { ldown[5]~498 ldown[5] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 49.74 % ) " "Info: Total cell delay = 2.191 ns ( 49.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.214 ns ( 50.26 % ) " "Info: Total interconnect delay = 2.214 ns ( 50.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "4.405 ns" { position[0] ldown[5]~495 ldown[5]~496 ldown[5]~498 ldown[5] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}