control.map.qmsg

VHDL编写的6层电梯控制器

{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "alarm~reg0 High " "Info: Power-up level of register \"alarm~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 13 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "alarm~reg0 data_in VCC " "Warning: Reduced register \"alarm~reg0\" with stuck data_in port to stuck value VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "lup\[0\] lup\[6\] " "Info: Duplicate register \"lup\[0\]\" merged to single register \"lup\[6\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lup\[4\] lup\[5\] " "Info: Duplicate register \"lup\[4\]\" merged to single register \"lup\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lup\[3\] lup\[5\] " "Info: Duplicate register \"lup\[3\]\" merged to single register \"lup\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lup\[2\] lup\[5\] " "Info: Duplicate register \"lup\[2\]\" merged to single register \"lup\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "lup\[1\] lup\[5\] " "Info: Duplicate register \"lup\[1\]\" merged to single register \"lup\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ldown\[1\] ldown\[6\] " "Info: Duplicate register \"ldown\[1\]\" merged to single register \"ldown\[6\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ldown\[4\] ldown\[5\] " "Info: Duplicate register \"ldown\[4\]\" merged to single register \"ldown\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ldown\[3\] ldown\[5\] " "Info: Duplicate register \"ldown\[3\]\" merged to single register \"ldown\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ldown\[2\] ldown\[5\] " "Info: Duplicate register \"ldown\[2\]\" merged to single register \"ldown\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "ldown\[0\] ldown\[5\] " "Info: Duplicate register \"ldown\[0\]\" merged to single register \"ldown\[5\]\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "lup\[6\] High " "Info: Power-up level of register \"lup\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "lup\[6\] data_in VCC " "Warning: Reduced register \"lup\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "ldown\[6\] High " "Info: Power-up level of register \"ldown\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "ldown\[6\] data_in VCC " "Warning: Reduced register \"ldown\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|control\|state 10 " "Info: State machine \"\|control\|state\" contains 10 states" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 38 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|control\|state " "Info: Selected Auto state machine encoding method for state machine \"\|control\|state\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 38 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|control\|state " "Info: Encoding result for state machine \"\|control\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "10 " "Info: Completed encoding using 10 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.dw5 " "Info: Encoded state bit \"state.dw5\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.dw4 " "Info: Encoded state bit \"state.dw4\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.dw3 " "Info: Encoded state bit \"state.dw3\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.dw2 " "Info: Encoded state bit \"state.dw2\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.dw1 " "Info: Encoded state bit \"state.dw1\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.stop " "Info: Encoded state bit \"state.stop\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.down2 " "Info: Encoded state bit \"state.down2\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.down1 " "Info: Encoded state bit \"state.down1\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.up2 " "Info: Encoded state bit \"state.up2\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.up1 " "Info: Encoded state bit \"state.up1\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.up1 0000000000 " "Info: State \"\|control\|state.up1\" uses code string \"0000000000\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.up2 0000000011 " "Info: State \"\|control\|state.up2\" uses code string \"0000000011\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.down1 0000000101 " "Info: State \"\|control\|state.down1\" uses code string \"0000000101\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.down2 0000001001 " "Info: State \"\|control\|state.down2\" uses code string \"0000001001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.stop 0000010001 " "Info: State \"\|control\|state.stop\" uses code string \"0000010001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.dw1 0000100001 " "Info: State \"\|control\|state.dw1\" uses code string \"0000100001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.dw2 0001000001 " "Info: State \"\|control\|state.dw2\" uses code string \"0001000001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.dw3 0010000001 " "Info: State \"\|control\|state.dw3\" uses code string \"0010000001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.dw4 0100000001 " "Info: State \"\|control\|state.dw4\" uses code string \"0100000001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|control\|state.dw5 1000000001 " "Info: State \"\|control\|state.dw5\" uses code string \"1000000001\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 38 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "alarm VCC " "Warning: Pin \"alarm\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "ovelight VCC " "Warning: Pin \"ovelight\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "locklight VCC " "Warning: Pin \"locklight\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 13 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lightup\[0\] VCC " "Warning: Pin \"lightup\[0\]\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lightup\[6\] VCC " "Warning: Pin \"lightup\[6\]\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lightdown\[1\] VCC " "Warning: Pin \"lightdown\[1\]\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lightdown\[6\] VCC " "Warning: Pin \"lightdown\[6\]\" stuck at VCC" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "lock " "Warning: No output dependent on input pin \"lock\"" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "103 " "Info: Implemented 103 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "71 " "Info: Implemented 71 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 09 20:50:25 2008 " "Info: Processing ended: Tue Sep 09 20:50:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}