control.tan.qmsg

VHDL编写的6层电梯控制器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register fl1 register ldown\[5\] 186.81 MHz 5.353 ns Internal " "Info: Clock \"clk\" has Internal fmax of 186.81 MHz between source register \"fl1\" and destination register \"ldown\[5\]\" (period= 5.353 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.121 ns + Longest register register " "Info: + Longest register to register delay is 5.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fl1 1 REG LC_X11_Y12_N4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N4; Fanout = 9; REG Node = 'fl1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { fl1 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.313 ns) + CELL(0.590 ns) 1.903 ns ldown\[5\]~495 2 COMB LC_X11_Y13_N8 1 " "Info: 2: + IC(1.313 ns) + CELL(0.590 ns) = 1.903 ns; Loc. = LC_X11_Y13_N8; Fanout = 1; COMB Node = 'ldown\[5\]~495'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.903 ns" { fl1 ldown[5]~495 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.442 ns) 2.753 ns ldown\[5\]~496 3 COMB LC_X11_Y13_N2 1 " "Info: 3: + IC(0.408 ns) + CELL(0.442 ns) = 2.753 ns; Loc. = LC_X11_Y13_N2; Fanout = 1; COMB Node = 'ldown\[5\]~496'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "0.850 ns" { ldown[5]~495 ldown[5]~496 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.590 ns) 3.788 ns ldown\[5\]~498 4 COMB LC_X11_Y13_N6 1 " "Info: 4: + IC(0.445 ns) + CELL(0.590 ns) = 3.788 ns; Loc. = LC_X11_Y13_N6; Fanout = 1; COMB Node = 'ldown\[5\]~498'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.035 ns" { ldown[5]~496 ldown[5]~498 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.867 ns) 5.121 ns ldown\[5\] 5 REG LC_X11_Y13_N4 5 " "Info: 5: + IC(0.466 ns) + CELL(0.867 ns) = 5.121 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.333 ns" { ldown[5]~498 ldown[5] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.489 ns ( 48.60 % ) " "Info: Total cell delay = 2.489 ns ( 48.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.632 ns ( 51.40 % ) " "Info: Total interconnect delay = 2.632 ns ( 51.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "5.121 ns" { fl1 ldown[5]~495 ldown[5]~496 ldown[5]~498 ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.121 ns" { fl1 ldown[5]~495 ldown[5]~496 ldown[5]~498 ldown[5] } { 0.000ns 1.313ns 0.408ns 0.445ns 0.466ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.029 ns - Smallest " "Info: - Smallest clock skew is 0.029 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 27 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { clk } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns ldown\[5\] 2 REG LC_X11_Y13_N4 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.485 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.954 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 ldown[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 27 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { clk } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns fl1 2 REG LC_X11_Y12_N4 9 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y12_N4; Fanout = 9; REG Node = 'fl1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.456 ns" { clk fl1 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk fl1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 fl1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.954 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 ldown[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk fl1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 fl1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "5.121 ns" { fl1 ldown[5]~495 ldown[5]~496 ldown[5]~498 ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.121 ns" { fl1 ldown[5]~495 ldown[5]~496 ldown[5]~498 ldown[5] } { 0.000ns 1.313ns 0.408ns 0.445ns 0.466ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.954 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 ldown[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk fl1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 fl1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "state.stop over clk 7.638 ns register " "Info: tsu for register \"state.stop\" (data pin = \"over\", clock pin = \"clk\") is 7.638 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.526 ns + Longest pin register " "Info: + Longest pin to register delay is 10.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns over 1 PIN PIN_219 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_219; Fanout = 3; PIN Node = 'over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { over } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.464 ns) + CELL(0.590 ns) 7.529 ns Select~2003 2 COMB LC_X12_Y14_N2 2 " "Info: 2: + IC(5.464 ns) + CELL(0.590 ns) = 7.529 ns; Loc. = LC_X12_Y14_N2; Fanout = 2; COMB Node = 'Select~2003'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "6.054 ns" { over Select~2003 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.590 ns) 9.361 ns state~482 3 COMB LC_X12_Y12_N6 1 " "Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 9.361 ns; Loc. = LC_X12_Y12_N6; Fanout = 1; COMB Node = 'state~482'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.832 ns" { Select~2003 state~482 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.738 ns) 10.526 ns state.stop 4 REG LC_X12_Y12_N5 7 " "Info: 4: + IC(0.427 ns) + CELL(0.738 ns) = 10.526 ns; Loc. = LC_X12_Y12_N5; Fanout = 7; REG Node = 'state.stop'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.165 ns" { state~482 state.stop } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.393 ns ( 32.23 % ) " "Info: Total cell delay = 3.393 ns ( 32.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.133 ns ( 67.77 % ) " "Info: Total interconnect delay = 7.133 ns ( 67.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "10.526 ns" { over Select~2003 state~482 state.stop } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.526 ns" { over over~out0 Select~2003 state~482 state.stop } { 0.000ns 0.000ns 5.464ns 1.242ns 0.427ns } { 0.000ns 1.475ns 0.590ns 0.590ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 27 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { clk } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns state.stop 2 REG LC_X12_Y12_N5 7 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y12_N5; Fanout = 7; REG Node = 'state.stop'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.456 ns" { clk state.stop } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk state.stop } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state.stop } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "10.526 ns" { over Select~2003 state~482 state.stop } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.526 ns" { over over~out0 Select~2003 state~482 state.stop } { 0.000ns 0.000ns 5.464ns 1.242ns 0.427ns } { 0.000ns 1.475ns 0.590ns 0.590ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk state.stop } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state.stop } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lightdown\[2\] ldown\[5\] 8.520 ns register " "Info: tco from clock \"clk\" to destination pin \"lightdown\[2\]\" through register \"ldown\[5\]\" is 8.520 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 27 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { clk } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns ldown\[5\] 2 REG LC_X11_Y13_N4 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.485 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.954 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 ldown[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.342 ns + Longest register pin " "Info: + Longest register to pin delay is 5.342 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ldown\[5\] 1 REG LC_X11_Y13_N4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { ldown[5] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.218 ns) + CELL(2.124 ns) 5.342 ns lightdown\[2\] 2 PIN PIN_21 0 " "Info: 2: + IC(3.218 ns) + CELL(2.124 ns) = 5.342 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'lightdown\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "5.342 ns" { ldown[5] lightdown[2] } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 39.76 % ) " "Info: Total cell delay = 2.124 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.218 ns ( 60.24 % ) " "Info: Total interconnect delay = 3.218 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "5.342 ns" { ldown[5] lightdown[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.342 ns" { ldown[5] lightdown[2] } { 0.000ns 3.218ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.954 ns" { clk ldown[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 ldown[5] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "5.342 ns" { ldown[5] lightdown[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.342 ns" { ldown[5] lightdown[2] } { 0.000ns 3.218ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "flag1 one clk -0.559 ns register " "Info: th for register \"flag1\" (data pin = \"one\", clock pin = \"clk\") is -0.559 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 27 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { clk } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns flag1 2 REG LC_X10_Y12_N2 2 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y12_N2; Fanout = 2; REG Node = 'flag1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "1.456 ns" { clk flag1 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk flag1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 flag1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.499 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns one 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'one'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "" { one } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.292 ns) + CELL(0.738 ns) 3.499 ns flag1 2 REG LC_X10_Y12_N2 2 " "Info: 2: + IC(1.292 ns) + CELL(0.738 ns) = 3.499 ns; Loc. = LC_X10_Y12_N2; Fanout = 2; REG Node = 'flag1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.030 ns" { one flag1 } "NODE_NAME" } "" } } { "Control.vhd" "" { Text "F:/08_Short Term/Control/Control.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 63.08 % ) " "Info: Total cell delay = 2.207 ns ( 63.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.292 ns ( 36.92 % ) " "Info: Total interconnect delay = 1.292 ns ( 36.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "3.499 ns" { one flag1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.499 ns" { one one~out0 flag1 } { 0.000ns 0.000ns 1.292ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "2.925 ns" { clk flag1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 flag1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Control" "UNKNOWN" "V1" "F:/08_Short Term/Control/db/Control.quartus_db" { Floorplan "F:/08_Short Term/Control/" "" "3.499 ns" { one flag1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.499 ns" { one one~out0 flag1 } { 0.000ns 0.000ns 1.292ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}