control.map.rpt

VHDL编写的6层电梯控制器

; Total registers                             ; 27    ;
; I/O pins                                    ; 32    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 27    ;
; Total fan-out                               ; 306   ;
; Average fan-out                             ; 2.97  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |control                   ; 71 (71)     ; 27           ; 0           ; 32   ; 0            ; 44 (44)      ; 2 (2)             ; 25 (25)          ; 0 (0)           ; 0 (0)      ; |control            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |control|state                                                                                                           ;
+-------------+-----------+-----------+-----------+-----------+-----------+------------+-------------+-------------+-----------+-----------+
; Name        ; state.dw5 ; state.dw4 ; state.dw3 ; state.dw2 ; state.dw1 ; state.stop ; state.down2 ; state.down1 ; state.up2 ; state.up1 ;
+-------------+-----------+-----------+-----------+-----------+-----------+------------+-------------+-------------+-----------+-----------+
; state.up1   ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0           ; 0           ; 0         ; 0         ;
; state.up2   ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0           ; 0           ; 1         ; 1         ;
; state.down1 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0           ; 1           ; 0         ; 1         ;
; state.down2 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0          ; 1           ; 0           ; 0         ; 1         ;
; state.stop  ; 0         ; 0         ; 0         ; 0         ; 0         ; 1          ; 0           ; 0           ; 0         ; 1         ;
; state.dw1   ; 0         ; 0         ; 0         ; 0         ; 1         ; 0          ; 0           ; 0           ; 0         ; 1         ;
; state.dw2   ; 0         ; 0         ; 0         ; 1         ; 0         ; 0          ; 0           ; 0           ; 0         ; 1         ;
; state.dw3   ; 0         ; 0         ; 1         ; 0         ; 0         ; 0          ; 0           ; 0           ; 0         ; 1         ;
; state.dw4   ; 0         ; 1         ; 0         ; 0         ; 0         ; 0          ; 0           ; 0           ; 0         ; 1         ;
; state.dw5   ; 1         ; 0         ; 0         ; 0         ; 0         ; 0          ; 0           ; 0           ; 0         ; 1         ;
+-------------+-----------+-----------+-----------+-----------+-----------+------------+-------------+-------------+-----------+-----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 3     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 21    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |control|\k1:cnt1[0]       ;
; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |control|lup[5]            ;
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; Yes        ; |control|ldown[5]          ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |control|state~122         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/08_Short Term/Control/Control.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Sep 09 20:50:22 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Control -c Control
Info: Found 2 design units, including 1 entities, in source file Control.vhd
    Info: Found design unit 1: control-behave
    Info: Found entity 1: control
Info: Elaborating entity "Control" for the top level hierarchy
Info: Power-up level of register "ala" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "ala" with stuck data_in port to stuck value VCC
Info: Power-up level of register "ov" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "ov" with stuck data_in port to stuck value VCC
Info: Power-up level of register "loc" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "loc" with stuck data_in port to stuck value VCC
Info: Power-up level of register "ovelight~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "ovelight~reg0" with stuck data_in port to stuck value VCC
Info: Power-up level of register "locklight~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "locklight~reg0" with stuck data_in port to stuck value VCC
Info: Power-up level of register "alarm~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "alarm~reg0" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "lup[0]" merged to single register "lup[6]"
    Info: Duplicate register "lup[4]" merged to single register "lup[5]"
    Info: Duplicate register "lup[3]" merged to single register "lup[5]"
    Info: Duplicate register "lup[2]" merged to single register "lup[5]"
    Info: Duplicate register "lup[1]" merged to single register "lup[5]"
    Info: Duplicate register "ldown[1]" merged to single register "ldown[6]"
    Info: Duplicate register "ldown[4]" merged to single register "ldown[5]"
    Info: Duplicate register "ldown[3]" merged to single register "ldown[5]"
    Info: Duplicate register "ldown[2]" merged to single register "ldown[5]"
    Info: Duplicate register "ldown[0]" merged to single register "ldown[5]"
Info: Power-up level of register "lup[6]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "lup[6]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "ldown[6]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "ldown[6]" with stuck data_in port to stuck value VCC
Info: State machine "|control|state" contains 10 states
Info: Selected Auto state machine encoding method for state machine "|control|state"
Info: Encoding result for state machine "|control|state"
    Info: Completed encoding using 10 state bits
        Info: Encoded state bit "state.dw5"
        Info: Encoded state bit "state.dw4"
        Info: Encoded state bit "state.dw3"
        Info: Encoded state bit "state.dw2"
        Info: Encoded state bit "state.dw1"
        Info: Encoded state bit "state.stop"
        Info: Encoded state bit "state.down2"
        Info: Encoded state bit "state.down1"
        Info: Encoded state bit "state.up2"
        Info: Encoded state bit "state.up1"
    Info: State "|control|state.up1" uses code string "0000000000"
    Info: State "|control|state.up2" uses code string "0000000011"
    Info: State "|control|state.down1" uses code string "0000000101"
    Info: State "|control|state.down2" uses code string "0000001001"
    Info: State "|control|state.stop" uses code string "0000010001"
    Info: State "|control|state.dw1" uses code string "0000100001"
    Info: State "|control|state.dw2" uses code string "0001000001"
    Info: State "|control|state.dw3" uses code string "0010000001"
    Info: State "|control|state.dw4" uses code string "0100000001"
    Info: State "|control|state.dw5" uses code string "1000000001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "alarm" stuck at VCC
    Warning: Pin "ovelight" stuck at VCC
    Warning: Pin "locklight" stuck at VCC
    Warning: Pin "lightup[0]" stuck at VCC
    Warning: Pin "lightup[6]" stuck at VCC
    Warning: Pin "lightdown[1]" stuck at VCC
    Warning: Pin "lightdown[6]" stuck at VCC
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "lock"
Info: Implemented 103 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 20 output pins
    Info: Implemented 71 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Tue Sep 09 20:50:25 2008
    Info: Elapsed time: 00:00:04