control.tan.rpt

VHDL编写的6层电梯控制器

; N/A           ; None        ; -4.582 ns ; three     ; flag3       ; clk      ;
; N/A           ; None        ; -4.690 ns ; downthree ; flag3       ; clk      ;
; N/A           ; None        ; -4.745 ns ; emergency ; state.dw1   ; clk      ;
; N/A           ; None        ; -4.837 ns ; downtwo   ; flag2       ; clk      ;
; N/A           ; None        ; -4.885 ns ; upone     ; flag1       ; clk      ;
; N/A           ; None        ; -4.888 ns ; reset     ; state.down2 ; clk      ;
; N/A           ; None        ; -4.975 ns ; reset     ; state.up1   ; clk      ;
; N/A           ; None        ; -5.006 ns ; uptwo     ; flag2       ; clk      ;
; N/A           ; None        ; -5.045 ns ; reset     ; \k1:cnt1[1] ; clk      ;
; N/A           ; None        ; -5.047 ns ; reset     ; \k1:cnt1[0] ; clk      ;
; N/A           ; None        ; -5.075 ns ; reset     ; state.dw1   ; clk      ;
; N/A           ; None        ; -5.187 ns ; over      ; state.dw1   ; clk      ;
; N/A           ; None        ; -5.350 ns ; two       ; flag2       ; clk      ;
; N/A           ; None        ; -5.452 ns ; reset     ; state.dw2   ; clk      ;
; N/A           ; None        ; -5.455 ns ; reset     ; state.dw3   ; clk      ;
; N/A           ; None        ; -5.557 ns ; reset     ; state.up2   ; clk      ;
; N/A           ; None        ; -5.682 ns ; reset     ; state.dw4   ; clk      ;
; N/A           ; None        ; -5.682 ns ; reset     ; position[1] ; clk      ;
; N/A           ; None        ; -5.739 ns ; reset     ; state.down1 ; clk      ;
; N/A           ; None        ; -5.739 ns ; reset     ; state.dw5   ; clk      ;
; N/A           ; None        ; -5.746 ns ; reset     ; ldown[5]    ; clk      ;
; N/A           ; None        ; -5.772 ns ; reset     ; lup[5]      ; clk      ;
; N/A           ; None        ; -6.056 ns ; reset     ; state.stop  ; clk      ;
; N/A           ; None        ; -6.095 ns ; emergency ; arr         ; clk      ;
; N/A           ; None        ; -6.144 ns ; reset     ; position[0] ; clk      ;
; N/A           ; None        ; -6.311 ns ; reset     ; \k1:updown  ; clk      ;
; N/A           ; None        ; -6.508 ns ; reset     ; fl2         ; clk      ;
; N/A           ; None        ; -6.569 ns ; over      ; arr         ; clk      ;
; N/A           ; None        ; -6.636 ns ; emergency ; ldown[5]    ; clk      ;
; N/A           ; None        ; -7.023 ns ; emergency ; lup[5]      ; clk      ;
; N/A           ; None        ; -7.108 ns ; reset     ; fl1         ; clk      ;
; N/A           ; None        ; -7.108 ns ; reset     ; clear2      ; clk      ;
; N/A           ; None        ; -7.108 ns ; reset     ; clear3      ; clk      ;
; N/A           ; None        ; -7.108 ns ; reset     ; clear1      ; clk      ;
; N/A           ; None        ; -7.112 ns ; emergency ; state.stop  ; clk      ;
; N/A           ; None        ; -7.189 ns ; over      ; ldown[5]    ; clk      ;
; N/A           ; None        ; -7.416 ns ; reset     ; arr         ; clk      ;
; N/A           ; None        ; -7.455 ns ; reset     ; fl3         ; clk      ;
; N/A           ; None        ; -7.576 ns ; over      ; lup[5]      ; clk      ;
; N/A           ; None        ; -7.586 ns ; over      ; state.stop  ; clk      ;
+---------------+-------------+-----------+-----------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Sep 09 20:50:40 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Control -c Control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 186.81 MHz between source register "fl1" and destination register "ldown[5]" (period= 5.353 ns)
    Info: + Longest register to register delay is 5.121 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N4; Fanout = 9; REG Node = 'fl1'
        Info: 2: + IC(1.313 ns) + CELL(0.590 ns) = 1.903 ns; Loc. = LC_X11_Y13_N8; Fanout = 1; COMB Node = 'ldown[5]~495'
        Info: 3: + IC(0.408 ns) + CELL(0.442 ns) = 2.753 ns; Loc. = LC_X11_Y13_N2; Fanout = 1; COMB Node = 'ldown[5]~496'
        Info: 4: + IC(0.445 ns) + CELL(0.590 ns) = 3.788 ns; Loc. = LC_X11_Y13_N6; Fanout = 1; COMB Node = 'ldown[5]~498'
        Info: 5: + IC(0.466 ns) + CELL(0.867 ns) = 5.121 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown[5]'
        Info: Total cell delay = 2.489 ns ( 48.60 % )
        Info: Total interconnect delay = 2.632 ns ( 51.40 % )
    Info: - Smallest clock skew is 0.029 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown[5]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "clk" to source register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y12_N4; Fanout = 9; REG Node = 'fl1'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "state.stop" (data pin = "over", clock pin = "clk") is 7.638 ns
    Info: + Longest pin to register delay is 10.526 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_219; Fanout = 3; PIN Node = 'over'
        Info: 2: + IC(5.464 ns) + CELL(0.590 ns) = 7.529 ns; Loc. = LC_X12_Y14_N2; Fanout = 2; COMB Node = 'Select~2003'
        Info: 3: + IC(1.242 ns) + CELL(0.590 ns) = 9.361 ns; Loc. = LC_X12_Y12_N6; Fanout = 1; COMB Node = 'state~482'
        Info: 4: + IC(0.427 ns) + CELL(0.738 ns) = 10.526 ns; Loc. = LC_X12_Y12_N5; Fanout = 7; REG Node = 'state.stop'
        Info: Total cell delay = 3.393 ns ( 32.23 % )
        Info: Total interconnect delay = 7.133 ns ( 67.77 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y12_N5; Fanout = 7; REG Node = 'state.stop'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: tco from clock "clk" to destination pin "lightdown[2]" through register "ldown[5]" is 8.520 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown[5]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.342 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y13_N4; Fanout = 5; REG Node = 'ldown[5]'
        Info: 2: + IC(3.218 ns) + CELL(2.124 ns) = 5.342 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'lightdown[2]'
        Info: Total cell delay = 2.124 ns ( 39.76 % )
        Info: Total interconnect delay = 3.218 ns ( 60.24 % )
Info: th for register "flag1" (data pin = "one", clock pin = "clk") is -0.559 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y12_N2; Fanout = 2; REG Node = 'flag1'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.499 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'one'
        Info: 2: + IC(1.292 ns) + CELL(0.738 ns) = 3.499 ns; Loc. = LC_X10_Y12_N2; Fanout = 2; REG Node = 'flag1'
        Info: Total cell delay = 2.207 ns ( 63.08 % )
        Info: Total interconnect delay = 1.292 ns ( 36.92 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Sep 09 20:50:41 2008
    Info: Elapsed time: 00:00:02