control.tan.rpt

VHDL编写的6层电梯控制器

Timing Analyzer report for Control
Tue Sep 09 20:50:41 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                  ;
+------------------------------+-------+---------------+----------------------------------+----------+--------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From     ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+--------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 7.638 ns                         ; over     ; state.stop   ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.520 ns                         ; ldown[5] ; lightdown[2] ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.559 ns                        ; one      ; flag1        ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 186.81 MHz ( period = 5.353 ns ) ; fl1      ; ldown[5]     ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;          ;              ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------+--------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                             ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From        ; To          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 186.81 MHz ( period = 5.353 ns )               ; fl1         ; ldown[5]    ; clk        ; clk      ; None                        ; None                      ; 5.121 ns                ;
; N/A   ; 191.06 MHz ( period = 5.234 ns )               ; position[0] ; ldown[5]    ; clk        ; clk      ; None                        ; None                      ; 5.002 ns                ;
; N/A   ; 195.81 MHz ( period = 5.107 ns )               ; position[1] ; lup[5]      ; clk        ; clk      ; None                        ; None                      ; 4.875 ns                ;
; N/A   ; 201.45 MHz ( period = 4.964 ns )               ; \k1:updown  ; ldown[5]    ; clk        ; clk      ; None                        ; None                      ; 4.703 ns                ;
; N/A   ; 201.49 MHz ( period = 4.963 ns )               ; state.dw4   ; lup[5]      ; clk        ; clk      ; None                        ; None                      ; 4.731 ns                ;
; N/A   ; 210.26 MHz ( period = 4.756 ns )               ; fl2         ; ldown[5]    ; clk        ; clk      ; None                        ; None                      ; 4.495 ns                ;
; N/A   ; 210.44 MHz ( period = 4.752 ns )               ; position[0] ; lup[5]      ; clk        ; clk      ; None                        ; None                      ; 4.520 ns                ;
; N/A   ; 214.22 MHz ( period = 4.668 ns )               ; state.dw5   ; lup[5]      ; clk        ; clk      ; None                        ; None                      ; 4.436 ns                ;
; N/A   ; 214.27 MHz ( period = 4.667 ns )               ; position[1] ; state.dw5   ; clk        ; clk      ; None                        ; None                      ; 4.406 ns                ;
; N/A   ; 214.96 MHz ( period = 4.652 ns )               ; position[1] ; state.down1 ; clk        ; clk      ; None                        ; None                      ; 4.391 ns                ;
; N/A   ; 215.52 MHz ( period = 4.640 ns )               ; fl2         ; clear3      ; clk        ; clk      ; None                        ; None                      ; 4.350 ns                ;
; N/A   ; 218.48 MHz ( period = 4.577 ns )               ; fl2         ; clear1      ; clk        ; clk      ; None                        ; None                      ; 4.287 ns                ;
; N/A   ; 219.01 MHz ( period = 4.566 ns )               ; state.dw4   ; ldown[5]    ; clk        ; clk      ; None                        ; None                      ; 4.334 ns                ;
; N/A   ; 219.59 MHz ( period = 4.554 ns )               ; state.stop  ; lup[5]      ; clk        ; clk      ; None                        ; None                      ; 4.322 ns                ;
; N/A   ; 221.09 MHz ( period = 4.523 ns )               ; state.dw4   ; state.dw5   ; clk        ; clk      ; None                        ; None                      ; 4.262 ns                ;
; N/A   ; 221.58 MHz ( period = 4.513 ns )               ; fl1         ; state.down1 ; clk        ; clk      ; None                        ; None                      ; 4.252 ns                ;
; N/A   ; 221.83 MHz ( period = 4.508 ns )               ; state.dw4   ; state.down1 ; clk        ; clk      ; None                        ; None                      ; 4.247 ns                ;
; N/A   ; 223.31 MHz ( period = 4.478 ns )               ; state.down2 ; clear3      ; clk        ; clk      ; None                        ; None                      ; 4.188 ns                ;
; N/A   ; 226.50 MHz ( period = 4.415 ns )               ; state.down2 ; clear1      ; clk        ; clk      ; None                        ; None                      ; 4.125 ns                ;
; N/A   ; 228.57 MHz ( period = 4.375 ns )               ; state.dw4   ; clear2      ; clk        ; clk      ; None                        ; None                      ; 4.114 ns                ;
; N/A   ; 229.04 MHz ( period = 4.366 ns )               ; position[1] ; ldown[5]    ; clk        ; clk      ; None                        ; None                      ; 4.134 ns                ;
; N/A   ; 229.46 MHz ( period = 4.358 ns )               ; position[1] ; state.up2   ; clk        ; clk      ; None                        ; None                      ; 4.126 ns                ;
; N/A   ; 230.47 MHz ( period = 4.339 ns )               ; position[0] ; fl2         ; clk        ; clk      ; None                        ; None                      ; 4.107 ns                ;
; N/A   ; 231.91 MHz ( period = 4.312 ns )               ; position[0] ; state.dw5   ; clk        ; clk      ; None                        ; None                      ; 4.051 ns                ;
; N/A   ; 232.40 MHz ( period = 4.303 ns )               ; state.up1   ; clear3      ; clk        ; clk      ; None                        ; None                      ; 4.013 ns                ;
; N/A   ; 232.72 MHz ( period = 4.297 ns )               ; position[0] ; state.down1 ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A   ; 233.64 MHz ( period = 4.280 ns )               ; fl2         ; lup[5]      ; clk        ; clk      ; None                        ; None                      ; 4.019 ns                ;
; N/A   ; 235.85 MHz ( period = 4.240 ns )               ; state.up1   ; clear1      ; clk        ; clk      ; None                        ; None                      ; 3.950 ns                ;