display.vhd

VHDL编写的6层电梯控制器

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 

entity display is
	port(clk	: in std_logic;
		 light	: in integer range 1 to 3;
		 serout	: out std_logic_vector(6 downto 0));
end;
architecture a of display is
	signal disp : std_logic_vector(6 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk='1')then
			if light =1 then
				disp<="1001111";
			elsif light=2 then
				disp<="0010010";
			elsif light=3 then 
				disp<="0000110";
			end if;
		end if;
	end process;
	serout<=disp;
end;