lift.tan.qmsg

VHDL编写的6层电梯控制器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register control:inst\|\\k1:cnt\[7\] register control:inst\|clear2 152.18 MHz 6.571 ns Internal " "Info: Clock \"clk\" has Internal fmax of 152.18 MHz between source register \"control:inst\|\\k1:cnt\[7\]\" and destination register \"control:inst\|clear2\" (period= 6.571 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.310 ns + Longest register register " "Info: + Longest register to register delay is 6.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:inst\|\\k1:cnt\[7\] 1 REG LC_X25_Y9_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y9_N0; Fanout = 4; REG Node = 'control:inst\|\\k1:cnt\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { control:inst|\k1:cnt[7] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.590 ns) 1.881 ns control:inst\|LessThan~352 2 COMB LC_X25_Y10_N3 1 " "Info: 2: + IC(1.291 ns) + CELL(0.590 ns) = 1.881 ns; Loc. = LC_X25_Y10_N3; Fanout = 1; COMB Node = 'control:inst\|LessThan~352'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.881 ns" { control:inst|\k1:cnt[7] control:inst|LessThan~352 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.414 ns) + CELL(0.442 ns) 2.737 ns control:inst\|LessThan~353 3 COMB LC_X25_Y10_N2 19 " "Info: 3: + IC(0.414 ns) + CELL(0.442 ns) = 2.737 ns; Loc. = LC_X25_Y10_N2; Fanout = 19; COMB Node = 'control:inst\|LessThan~353'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "0.856 ns" { control:inst|LessThan~352 control:inst|LessThan~353 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.590 ns) 3.784 ns control:inst\|fl1~2 4 COMB LC_X25_Y10_N4 8 " "Info: 4: + IC(0.457 ns) + CELL(0.590 ns) = 3.784 ns; Loc. = LC_X25_Y10_N4; Fanout = 8; COMB Node = 'control:inst\|fl1~2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.047 ns" { control:inst|LessThan~353 control:inst|fl1~2 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.867 ns) 6.310 ns control:inst\|clear2 5 REG LC_X24_Y7_N4 2 " "Info: 5: + IC(1.659 ns) + CELL(0.867 ns) = 6.310 ns; Loc. = LC_X24_Y7_N4; Fanout = 2; REG Node = 'control:inst\|clear2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.526 ns" { control:inst|fl1~2 control:inst|clear2 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.489 ns ( 39.45 % ) " "Info: Total cell delay = 2.489 ns ( 39.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.821 ns ( 60.55 % ) " "Info: Total interconnect delay = 3.821 ns ( 60.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "6.310 ns" { control:inst|\k1:cnt[7] control:inst|LessThan~352 control:inst|LessThan~353 control:inst|fl1~2 control:inst|clear2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.310 ns" { control:inst|\k1:cnt[7] control:inst|LessThan~352 control:inst|LessThan~353 control:inst|fl1~2 control:inst|clear2 } { 0.000ns 1.291ns 0.414ns 0.457ns 1.659ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.910 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { clk } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -48 -488 -320 -32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns control:inst\|clear2 2 REG LC_X24_Y7_N4 2 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X24_Y7_N4; Fanout = 2; REG Node = 'control:inst\|clear2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.441 ns" { clk control:inst|clear2 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.91 % ) " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk control:inst|clear2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 control:inst|clear2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.910 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { clk } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -48 -488 -320 -32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns control:inst\|\\k1:cnt\[7\] 2 REG LC_X25_Y9_N0 4 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X25_Y9_N0; Fanout = 4; REG Node = 'control:inst\|\\k1:cnt\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.441 ns" { clk control:inst|\k1:cnt[7] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.91 % ) " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk control:inst|\k1:cnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 control:inst|\k1:cnt[7] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk control:inst|clear2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 control:inst|clear2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk control:inst|\k1:cnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 control:inst|\k1:cnt[7] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 38 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "6.310 ns" { control:inst|\k1:cnt[7] control:inst|LessThan~352 control:inst|LessThan~353 control:inst|fl1~2 control:inst|clear2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.310 ns" { control:inst|\k1:cnt[7] control:inst|LessThan~352 control:inst|LessThan~353 control:inst|fl1~2 control:inst|clear2 } { 0.000ns 1.291ns 0.414ns 0.457ns 1.659ns } { 0.000ns 0.590ns 0.442ns 0.590ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk control:inst|clear2 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 control:inst|clear2 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk control:inst|\k1:cnt[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 control:inst|\k1:cnt[7] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "unshake:inst16\|cp over clk 6.685 ns register " "Info: tsu for register \"unshake:inst16\|cp\" (data pin = \"over\", clock pin = \"clk\") is 6.685 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.590 ns + Longest pin register " "Info: + Longest pin to register delay is 9.590 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns over 1 PIN PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 3; PIN Node = 'over'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { over } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 312 -152 16 328 "over" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.643 ns) + CELL(0.478 ns) 9.590 ns unshake:inst16\|cp 2 REG LC_X24_Y10_N1 4 " "Info: 2: + IC(7.643 ns) + CELL(0.478 ns) = 9.590 ns; Loc. = LC_X24_Y10_N1; Fanout = 4; REG Node = 'unshake:inst16\|cp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "8.121 ns" { over unshake:inst16|cp } "NODE_NAME" } "" } } { "unshake.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/unshake.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 20.30 % ) " "Info: Total cell delay = 1.947 ns ( 20.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.643 ns ( 79.70 % ) " "Info: Total interconnect delay = 7.643 ns ( 79.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "9.590 ns" { over unshake:inst16|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.590 ns" { over over~out0 unshake:inst16|cp } { 0.000ns 0.000ns 7.643ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "unshake.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/unshake.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { clk } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -48 -488 -320 -32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns unshake:inst16\|cp 2 REG LC_X24_Y10_N1 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X24_Y10_N1; Fanout = 4; REG Node = 'unshake:inst16\|cp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.473 ns" { clk unshake:inst16|cp } "NODE_NAME" } "" } } { "unshake.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/unshake.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.942 ns" { clk unshake:inst16|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 unshake:inst16|cp } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "9.590 ns" { over unshake:inst16|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.590 ns" { over over~out0 unshake:inst16|cp } { 0.000ns 0.000ns 7.643ns } { 0.000ns 1.469ns 0.478ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.942 ns" { clk unshake:inst16|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 unshake:inst16|cp } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lightup\[2\] control:inst\|lup\[5\] 8.743 ns register " "Info: tco from clock \"clk\" to destination pin \"lightup\[2\]\" through register \"control:inst\|lup\[5\]\" is 8.743 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { clk } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -48 -488 -320 -32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns control:inst\|lup\[5\] 2 REG LC_X24_Y10_N9 5 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X24_Y10_N9; Fanout = 5; REG Node = 'control:inst\|lup\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.473 ns" { clk control:inst|lup[5] } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.942 ns" { clk control:inst|lup[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 control:inst|lup[5] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.577 ns + Longest register pin " "Info: + Longest register to pin delay is 5.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:inst\|lup\[5\] 1 REG LC_X24_Y10_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y10_N9; Fanout = 5; REG Node = 'control:inst\|lup\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { control:inst|lup[5] } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.469 ns) + CELL(2.108 ns) 5.577 ns lightup\[2\] 2 PIN PIN_83 0 " "Info: 2: + IC(3.469 ns) + CELL(2.108 ns) = 5.577 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'lightup\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "5.577 ns" { control:inst|lup[5] lightup[2] } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 112 424 600 128 "lightup\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 37.80 % ) " "Info: Total cell delay = 2.108 ns ( 37.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.469 ns ( 62.20 % ) " "Info: Total interconnect delay = 3.469 ns ( 62.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "5.577 ns" { control:inst|lup[5] lightup[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.577 ns" { control:inst|lup[5] lightup[2] } { 0.000ns 3.469ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.942 ns" { clk control:inst|lup[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 control:inst|lup[5] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "5.577 ns" { control:inst|lup[5] lightup[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.577 ns" { control:inst|lup[5] lightup[2] } { 0.000ns 3.469ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "unshake:inst14\|cp three clk -3.727 ns register " "Info: th for register \"unshake:inst14\|cp\" (data pin = \"three\", clock pin = \"clk\") is -3.727 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { clk } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -48 -488 -320 -32 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns unshake:inst14\|cp 2 REG LC_X34_Y7_N9 2 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X34_Y7_N9; Fanout = 2; REG Node = 'unshake:inst14\|cp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.441 ns" { clk unshake:inst14|cp } "NODE_NAME" } "" } } { "unshake.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/unshake.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.91 % ) " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk unshake:inst14|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 unshake:inst14|cp } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "unshake.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/unshake.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.652 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns three 1 PIN PIN_138 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_138; Fanout = 3; PIN Node = 'three'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { three } "NODE_NAME" } "" } } { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 120 -152 16 136 "three" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.576 ns) + CELL(0.607 ns) 6.652 ns unshake:inst14\|cp 2 REG LC_X34_Y7_N9 2 " "Info: 2: + IC(4.576 ns) + CELL(0.607 ns) = 6.652 ns; Loc. = LC_X34_Y7_N9; Fanout = 2; REG Node = 'unshake:inst14\|cp'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "5.183 ns" { three unshake:inst14|cp } "NODE_NAME" } "" } } { "unshake.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/unshake.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 31.21 % ) " "Info: Total cell delay = 2.076 ns ( 31.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.576 ns ( 68.79 % ) " "Info: Total interconnect delay = 4.576 ns ( 68.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "6.652 ns" { three unshake:inst14|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.652 ns" { three three~out0 unshake:inst14|cp } { 0.000ns 0.000ns 4.576ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.910 ns" { clk unshake:inst14|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { clk clk~out0 unshake:inst14|cp } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "6.652 ns" { three unshake:inst14|cp } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.652 ns" { three three~out0 unshake:inst14|cp } { 0.000ns 0.000ns 4.576ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}