lift.fit.qmsg

VHDL编写的6层电梯控制器

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.30 0 3 0 " "Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 0 input, 3 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 6 38 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 6 total pin(s) used --  38 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 1 47 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used --  47 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 8 37 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 8 total pin(s) used --  37 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 21 27 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 21 total pin(s) used --  27 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.186 ns register register " "Info: Estimated most critical path is register to register delay of 5.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:inst\|\\k1:cnt\[16\] 1 REG LAB_X25_Y10 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y10; Fanout = 6; REG Node = 'control:inst\|\\k1:cnt\[16\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { control:inst|\k1:cnt[16] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.875 ns) + CELL(0.590 ns) 1.465 ns control:inst\|LessThan~354 2 COMB LAB_X26_Y8 19 " "Info: 2: + IC(0.875 ns) + CELL(0.590 ns) = 1.465 ns; Loc. = LAB_X26_Y8; Fanout = 19; COMB Node = 'control:inst\|LessThan~354'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.465 ns" { control:inst|\k1:cnt[16] control:inst|LessThan~354 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(0.292 ns) 2.854 ns control:inst\|fl1~2 3 COMB LAB_X25_Y10 8 " "Info: 3: + IC(1.097 ns) + CELL(0.292 ns) = 2.854 ns; Loc. = LAB_X25_Y10; Fanout = 8; COMB Node = 'control:inst\|fl1~2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "1.389 ns" { control:inst|LessThan~354 control:inst|fl1~2 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.465 ns) + CELL(0.867 ns) 5.186 ns control:inst\|fl2 4 REG LAB_X23_Y9 14 " "Info: 4: + IC(1.465 ns) + CELL(0.867 ns) = 5.186 ns; Loc. = LAB_X23_Y9; Fanout = 14; REG Node = 'control:inst\|fl2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "2.332 ns" { control:inst|fl1~2 control:inst|fl2 } "NODE_NAME" } "" } } { "control.vhd" "" { Text "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/control.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.749 ns ( 33.73 % ) " "Info: Total cell delay = 1.749 ns ( 33.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.437 ns ( 66.27 % ) " "Info: Total interconnect delay = 3.437 ns ( 66.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "5.186 ns" { control:inst|\k1:cnt[16] control:inst|LessThan~354 control:inst|fl1~2 control:inst|fl2 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "locklight VCC " "Info: Pin locklight has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 80 424 600 96 "locklight" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "locklight" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { locklight } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { locklight } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ovelight VCC " "Info: Pin ovelight has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 64 424 600 80 "ovelight" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ovelight" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { ovelight } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { ovelight } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "alarm VCC " "Info: Pin alarm has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 48 424 600 64 "alarm" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "alarm" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { alarm } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { alarm } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lightdown\[6\] VCC " "Info: Pin lightdown\[6\] has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 128 424 600 144 "lightdown\[6..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lightdown\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { lightdown[6] } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { lightdown[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lightdown\[1\] VCC " "Info: Pin lightdown\[1\] has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 128 424 600 144 "lightdown\[6..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lightdown\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { lightdown[1] } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { lightdown[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lightup\[6\] VCC " "Info: Pin lightup\[6\] has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 112 424 600 128 "lightup\[6..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lightup\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { lightup[6] } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { lightup[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lightup\[0\] VCC " "Info: Pin lightup\[0\] has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { 112 424 600 128 "lightup\[6..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lightup\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { lightup[0] } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { lightup[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "serout\[5\] GND " "Info: Pin serout\[5\] has GND driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -56 696 872 -40 "serout\[6..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "serout\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { serout[5] } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { serout[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "serout\[1\] VCC " "Info: Pin serout\[1\] has VCC driving its datain port" {  } { { "Lift.bdf" "" { Schematic "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.bdf" { { -56 696 872 -40 "serout\[6..0\]" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "serout\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "Lift" "UNKNOWN" "V1" "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/db/Lift.quartus_db" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/" "" "" { serout[1] } "NODE_NAME" } "" } } { "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" { Floorplan "F:/08_Short Term/数字系统设计/Lift (Ultimate_Version)/Lift.fld" "" "" { serout[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 10 00:27:56 2008 " "Info: Processing ended: Wed Sep 10 00:27:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}