unshake.vhd

VHDL编写的6层电梯控制器

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 

entity unshake is 
port(clk	:in std_logic;    --时钟，10HZ；
	 key	:in std_logic;    --开关信号；
	 keyout	:out std_logic);  --消抖之后的开关信号
end;
architecture a of unshake is 
	signal cp :std_logic;
	signal jsp:integer range 0 to 3;
begin
	process(clk)
	begin
		if(clk'event and clk='1')then
			if key='1' then
				if jsp=3 then
					jsp<=jsp;
				else
					jsp<=jsp+1;
				end if;
				if jsp=1 then
					cp<='1';
				else
					cp<='0';
				end if;
			else
				jsp<=0;
			end if;
		end if;
	keyout<=cp;
	end process;
end;