📄 fifo_1.sim.rpt
字号:
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita1~COUT ; cout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita2 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_reg_bit4a[2] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|safe_q[2] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_reg_bit4a[1] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|safe_q[1] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_reg_bit4a[0] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|safe_q[0] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita0 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita0~COUT ; cout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita1 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita1~COUT ; cout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_comb_bita2 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_reg_bit4a[2] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|safe_q[2] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_reg_bit4a[1] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|safe_q[1] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|counter_reg_bit4a[0] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count|safe_q[0] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|ram_block3a1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|q_b[1] ; portbdataout0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|ram_block3a2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|q_b[2] ; portbdataout0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~1 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~2 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~4 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~4 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~6 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~6 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~8 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~8 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~10 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~10 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_full~1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_full~1 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~17 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~17 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~19 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~19 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~21 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~21 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~22 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~22 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~24 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~24 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~26 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~26 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~27 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~27 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_non_empty~1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_non_empty~1 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~28 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|_~28 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_empty1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_empty1 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_empty2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_empty2 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_full1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_full1 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_full2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|is_almost_full2 ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|valid_rreq ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|valid_rreq ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_full ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_full ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_non_empty ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|b_non_empty ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita0 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita0~COUT ; cout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita1 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita1 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita1~COUT ; cout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita2 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_comb_bita2 ; combout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_reg_bit1a[2] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|safe_q[2] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_reg_bit1a[1] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|safe_q[1] ; regout ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|counter_reg_bit1a[0] ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw|safe_q[0] ; regout ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |FIFO_1|wr ; |FIFO_1|wr ; out ;
; |FIFO_1|din[7] ; |FIFO_1|din[7] ; out ;
; |FIFO_1|din[6] ; |FIFO_1|din[6] ; out ;
; |FIFO_1|din[5] ; |FIFO_1|din[5] ; out ;
; |FIFO_1|din[4] ; |FIFO_1|din[4] ; out ;
; |FIFO_1|din[0] ; |FIFO_1|din[0] ; out ;
; |FIFO_1|dout[7] ; |FIFO_1|dout[7] ; pin_out ;
; |FIFO_1|dout[6] ; |FIFO_1|dout[6] ; pin_out ;
; |FIFO_1|dout[5] ; |FIFO_1|dout[5] ; pin_out ;
; |FIFO_1|dout[4] ; |FIFO_1|dout[4] ; pin_out ;
; |FIFO_1|dout[0] ; |FIFO_1|dout[0] ; pin_out ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|valid_wreq ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|valid_wreq ; out0 ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|ram_block3a0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|q_b[0] ; portbdataout0 ;
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