a_fefifo_n4e.tdf

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=8 lpm_widthad=3 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock empty full rreq sclr wreq
--VERSION_BEGIN 7.0 cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_fifo_common 2006:03:14:10:59:42:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_counter 2006:11:07:16:43:46:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ  VERSION_END


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FUNCTION cntr_oj7 (aclr, clock, cnt_en, sclr, updown)
RETURNS ( q[2..0]);

--synthesis_resources = lut 3 reg 5 
SUBDESIGN a_fefifo_n4e
( 
	aclr	:	input;
	clock	:	input;
	empty	:	output;
	full	:	output;
	rreq	:	input;
	sclr	:	input;
	wreq	:	input;
) 
VARIABLE 
	b_full : dffe;
	b_non_empty : dffe;
	count_usedw : cntr_oj7;
	equal_af1w[2..0]	: WIRE;
	equal_one[2..0]	: WIRE;
	is_almost_empty0	: WIRE;
	is_almost_empty1	: WIRE;
	is_almost_empty2	: WIRE;
	is_almost_full0	: WIRE;
	is_almost_full1	: WIRE;
	is_almost_full2	: WIRE;
	usedw[2..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	b_full.clk = clock;
	b_full.clrn = (! aclr);
	b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full2 & wreq) & (! rreq)))));
	b_non_empty.clk = clock;
	b_non_empty.clrn = (! aclr);
	b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty2 & rreq) & (! wreq))))));
	count_usedw.aclr = aclr;
	count_usedw.clock = clock;
	count_usedw.cnt_en = (valid_wreq $ valid_rreq);
	count_usedw.sclr = sclr;
	count_usedw.updown = valid_wreq;
	empty = (! b_non_empty.q);
	equal_af1w[] = ( B"0", B"0", B"0");
	equal_one[] = ( B"1", B"1", B"0");
	full = b_full.q;
	is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]);
	is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0);
	is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1);
	is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]);
	is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0);
	is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1);
	usedw[] = count_usedw.q[];
	valid_rreq = (rreq & b_non_empty.q);
	valid_wreq = (wreq & (! b_full.q));
END;
--VALID FILE